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Reduce the target entry points to the target_design.

This commit is contained in:
steve 2000-10-21 16:49:45 +00:00
parent ecf71efc84
commit add2ae16fa
5 changed files with 45 additions and 195 deletions
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62
ivl_target.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: ivl_target.h,v 1.21 2000/10/18 20:04:39 steve Exp $"
#ident "$Id: ivl_target.h,v 1.22 2000/10/21 16:49:45 steve Exp $"
#endif
#ifdef __cplusplus
@ -489,66 +489,26 @@ extern ivl_expr_t ivl_stmt_rval(ivl_statement_t net);
extern ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net);
/* TARGET MODULE ENTRY POINTS
*
* These are not functions in the API but functions that the target
* module supplies. They are presented as typedefs of functions (which
* are used internally) but the target module makes them work by
* exporting them.
*
* The module entry points generally take a cookie and possibly a name
* as parameters. They use the cookie to get the required detailed
* information, and they do their job. The functions return an integer
* value which usually should be 0 for success, or less then 0 for any
* errors. How the error is interpreted depends on the function
* returning the error.
*/
/* target_start_design (required)
/* target_design
The "target_start_design" function is called once before
any other functions in order to start the processing of the
netlist. The function returns a value <0 if there is an error. */
typedef int (*start_design_f)(ivl_design_t des);
The "target_design" function is called once after the whole design
is processed and available to the target. The target doesn't return
from this function until it is finished with the design.
This function is implemented in the loaded target, and not in the
ivl core. This function is how the target module is invoked. */
/* target_end_design (required)
The target_end_design function in the loaded module is called once
to clean up (for example to close files) from handling of the
netlist. */
typedef void (*end_design_f)(ivl_design_t des);
/* target_net_const (optional)
The "target_net_const" function is called for structural constant
values that appear in the design. */
typedef int (*net_const_f)(const char*name, ivl_net_const_t net);
/* target_net_event
Verilog code such as @event and @(posedge foo) create event
objects. These named objects can be triggered by structural probes
or behavioral triggers. The target_net_event function is called
once for each event in the netlist. The event function is
guaranteed to be called before probe or trigger functions. */
typedef int (*net_event_f)(const char*name, ivl_net_event_t net);
/* target_net_probe
This is the probe, or structural trigger, of an event. The
net_event_f is guaranteed to be called for the associated event
before this probe is called. */
typedef int (*net_probe_f)(const char*name, ivl_net_probe_t net);
typedef int (*target_design_f)(ivl_design_t des);
_END_DECL
/*
* $Log: ivl_target.h,v $
* Revision 1.22 2000/10/21 16:49:45 steve
* Reduce the target entry points to the target_design.
*
* Revision 1.21 2000/10/18 20:04:39 steve
* Add ivl_lval_t and support for assignment l-values.
*

83
t-dll.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: t-dll.cc,v 1.15 2000/10/15 04:46:23 steve Exp $"
#ident "$Id: t-dll.cc,v 1.16 2000/10/21 16:49:45 steve Exp $"
#endif
# include "compiler.h"
@ -132,14 +132,13 @@ bool dll_target::start_design(const Design*des)
des_.root_ = new struct ivl_scope_s;
des_.root_->name_ = strdup(des->find_root_scope()->name().c_str());
start_design_ = (start_design_f)dlsym(dll_, LU "target_start_design" TU);
end_design_ = (end_design_f) dlsym(dll_, LU "target_end_design" TU);
target_ = (target_design_f)dlsym(dll_, LU "target_design" TU);
if (target_ == 0) {
cerr << dll_path_ << ": error: target_design entry "
"point is missing." << endl;
return false;
}
net_const_ = (net_const_f) dlsym(dll_, LU "target_net_const" TU);
net_event_ = (net_event_f) dlsym(dll_, LU "target_net_event" TU);
net_probe_ = (net_probe_f) dlsym(dll_, LU "target_net_probe" TU);
(start_design_)(&des_);
return true;
}
@ -149,7 +148,7 @@ bool dll_target::start_design(const Design*des)
*/
void dll_target::end_design(const Design*)
{
(end_design_)(&des_);
(target_)(&des_);
dlclose(dll_);
}
@ -201,15 +200,6 @@ bool dll_target::bufz(const NetBUFZ*net)
void dll_target::event(const NetEvent*net)
{
if (net_event_) {
(net_event_)(net->full_name().c_str(), 0);
} else {
cerr << dll_path_ << ": internal error: target DLL lacks "
<< "target_net_event function." << endl;
}
return;
}
void dll_target::logic(const NetLogic*net)
@ -257,6 +247,14 @@ void dll_target::logic(const NetLogic*net)
scope_add_logic(scope, obj);
}
/*
* The assignment l-values are captured by the assignment statements
* themselves in the process handling.
*/
void dll_target::net_assign(const NetAssign_*)
{
}
bool dll_target::net_const(const NetConst*net)
{
unsigned idx;
@ -308,28 +306,11 @@ bool dll_target::net_const(const NetConst*net)
}
}
/* All done, call the target_net_const function if it exists. */
if (net_const_) {
int rc = (net_const_)(net->name(), obj);
return rc == 0;
}
return true;
}
void dll_target::net_probe(const NetEvProbe*net)
{
if (net_probe_) {
int rc = (net_probe_)(net->name(), 0);
return;
} else {
cerr << dll_path_ << ": internal error: target DLL lacks "
<< "target_net_probe function." << endl;
return;
}
return;
}
void dll_target::scope(const NetScope*net)
@ -513,6 +494,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
/*
* $Log: t-dll.cc,v $
* Revision 1.16 2000/10/21 16:49:45 steve
* Reduce the target entry points to the target_design.
*
* Revision 1.15 2000/10/15 04:46:23 steve
* Scopes and processes are accessible randomly from
* the design, and signals and logic are accessible
@ -548,34 +532,5 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
* Revision 1.9 2000/09/30 02:18:15 steve
* ivl_expr_t support for binary operators,
* Create a proper ivl_scope_t object.
*
* Revision 1.8 2000/09/24 15:46:00 steve
* API access to signal type and port type.
*
* Revision 1.7 2000/09/18 01:24:32 steve
* Get the structure for ivl_statement_t worked out.
*
* Revision 1.6 2000/08/27 15:51:51 steve
* t-dll iterates signals, and passes them to the
* target module.
*
* Some of NetObj should return char*, not string.
*
* Revision 1.5 2000/08/26 00:54:03 steve
* Get at gate information for ivl_target interface.
*
* Revision 1.4 2000/08/20 04:13:57 steve
* Add ivl_target support for logic gates, and
* make the interface more accessible.
*
* Revision 1.3 2000/08/19 18:12:42 steve
* Add target calls for scope, events and logic.
*
* Revision 1.2 2000/08/14 04:39:57 steve
* add th t-dll functions for net_const, net_bufz and processes.
*
* Revision 1.1 2000/08/12 16:34:37 steve
* Start stub for loadable targets.
*
*/

12
t-dll.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: t-dll.h,v 1.14 2000/10/18 20:04:39 steve Exp $"
#ident "$Id: t-dll.h,v 1.15 2000/10/21 16:49:45 steve Exp $"
#endif
# include "target.h"
@ -49,6 +49,7 @@ struct dll_target : public target_t, public expr_scan_t {
bool bufz(const NetBUFZ*);
void event(const NetEvent*);
void logic(const NetLogic*);
void net_assign(const NetAssign_*);
bool net_const(const NetConst*);
void net_probe(const NetEvProbe*);
@ -61,12 +62,8 @@ struct dll_target : public target_t, public expr_scan_t {
ivl_design_s des_;
start_design_f start_design_;
end_design_f end_design_;
target_design_f target_;
net_const_f net_const_;
net_event_f net_event_;
net_probe_f net_probe_;
/* These methods and members are used for forming the
statements of a thread. */
@ -313,6 +310,9 @@ struct ivl_statement_s {
/*
* $Log: t-dll.h,v $
* Revision 1.15 2000/10/21 16:49:45 steve
* Reduce the target entry points to the target_design.
*
* Revision 1.14 2000/10/18 20:04:39 steve
* Add ivl_lval_t and support for assignment l-values.
*

42
tgt-stub/stub.c
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@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: stub.c,v 1.19 2000/10/18 20:04:39 steve Exp $"
#ident "$Id: stub.c,v 1.20 2000/10/21 16:49:45 steve Exp $"
#endif
/*
@ -271,7 +271,7 @@ static int show_scope(ivl_scope_t net)
return ivl_scope_children(net, show_scope);
}
int target_start_design(ivl_design_t des)
int target_design(ivl_design_t des)
{
const char*path = ivl_design_flag(des, "-o");
if (path == 0) {
@ -286,46 +286,11 @@ int target_start_design(ivl_design_t des)
fprintf(out, "root module = %s;\n",
ivl_scope_name(ivl_design_root(des)));
return 0;
}
void target_end_design(ivl_design_t des)
{
show_scope(ivl_design_root(des));
ivl_design_process(des, show_process);
fclose(out);
}
int target_net_const(const char*name, ivl_net_const_t net)
{
unsigned idx;
unsigned wid = ivl_const_pins(net);
const char*bits = ivl_const_bits(net);
fprintf(out, "LPM_CONSTANT %s: %s%u'b", name,
ivl_const_signed(net)? "+- ":"",
wid);
for (idx = 0 ; idx < wid ; idx += 1)
fprintf(out, "%c", bits[wid-1-idx]);
fprintf(out, " (%s", ivl_nexus_name(ivl_const_pin(net, 0)));
for (idx = 1 ; idx < wid ; idx += 1)
fprintf(out, ", %s", ivl_nexus_name(ivl_const_pin(net, idx)));
fprintf(out, ")\n");
return 0;
}
int target_net_event(const char*name, ivl_net_event_t net)
{
fprintf(out, "STUB: %s: event\n", name);
return 0;
}
int target_net_probe(const char*name, ivl_net_probe_t net)
{
fprintf(out, "STUB: %s: probe\n", name);
return 0;
}
@ -336,6 +301,9 @@ DECLARE_CYGWIN_DLL(DllMain);
/*
* $Log: stub.c,v $
* Revision 1.20 2000/10/21 16:49:45 steve
* Reduce the target entry points to the target_design.
*
* Revision 1.19 2000/10/18 20:04:39 steve
* Add ivl_lval_t and support for assignment l-values.
*

41
tgt-verilog/verilog.c
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT) && !defined(macintosh)
#ident "$Id: verilog.c,v 1.12 2000/10/15 21:02:09 steve Exp $"
#ident "$Id: verilog.c,v 1.13 2000/10/21 16:49:45 steve Exp $"
#endif
/*
@ -209,18 +209,6 @@ void target_end_design(ivl_design_t des)
fclose(out);
}
int target_net_const(const char*name, ivl_net_const_t net)
{
fprintf(out, "STUB: %s: constant\n", name);
return 0;
}
int target_net_event(const char*name, ivl_net_event_t net)
{
fprintf(out, "STUB: %s: event\n", name);
return 0;
}
int target_net_logic(const char*name, ivl_net_logic_t net)
{
unsigned npins, idx;
@ -262,30 +250,6 @@ int target_net_probe(const char*name, ivl_net_probe_t net)
return 0;
}
int target_net_signal(const char*name, ivl_signal_t net)
{
unsigned cnt = ivl_signal_pins(net);
switch (ivl_signal_type(net)) {
case IVL_SIT_REG:
fprintf(out, " reg [%u:0] %s; // %s\n", cnt-1,
ivl_signal_basename(net), name);
break;
case IVL_SIT_WIRE:
fprintf(out, " wire [%u:0] %s; // %s\n", cnt-1,
ivl_signal_basename(net), name);
break;
default:
fprintf(out, " <huh!?> [%u:0] %s;\n", cnt-1, name);
break;
}
return 0;
}
#ifdef __CYGWIN32__
#include <cygwin/cygwin_dll.h>
DECLARE_CYGWIN_DLL(DllMain);
@ -293,6 +257,9 @@ DECLARE_CYGWIN_DLL(DllMain);
/*
* $Log: verilog.c,v $
* Revision 1.13 2000/10/21 16:49:45 steve
* Reduce the target entry points to the target_design.
*
* Revision 1.12 2000/10/15 21:02:09 steve
* Makefile patches to support target loading under cygwin.
*