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Separate the virtex and generic-edif code generators.

This commit is contained in:
steve 2001-09-06 04:28:39 +00:00
parent 298a352cbd
commit acde444439
6 changed files with 332 additions and 82 deletions
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4
tgt-fpga/Makefile.in
View File

@ -16,7 +16,7 @@
# 59 Temple Place - Suite 330 # 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA # Boston, MA 02111-1307, USA
# #
#ident "$Id: Makefile.in,v 1.2 2001/09/02 21:33:07 steve Exp $" #ident "$Id: Makefile.in,v 1.3 2001/09/06 04:28:39 steve Exp $"
# #
# #
SHELL = /bin/sh SHELL = /bin/sh
@ -49,7 +49,7 @@ all: fpga.tgt
$(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o $(CC) -Wall -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
mv $*.d dep mv $*.d dep
D = d-generic.o d-generic-edif.o D = d-generic.o d-generic-edif.o d-virtex.o
O = fpga.o gates.o mangle.o tables.o $D O = fpga.o gates.o mangle.o tables.o $D
ifeq (@WIN32@,yes) ifeq (@WIN32@,yes)

152
tgt-fpga/d-generic-edif.c
View File

@ -16,7 +16,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ident "$Id: d-generic-edif.c,v 1.2 2001/09/02 23:53:55 steve Exp $" #ident "$Id: d-generic-edif.c,v 1.3 2001/09/06 04:28:40 steve Exp $"
# include "device.h" # include "device.h"
# include "fpga_priv.h" # include "fpga_priv.h"
@ -32,9 +32,9 @@ struct nexus_recall {
}; };
static struct nexus_recall*net_list = 0; static struct nexus_recall*net_list = 0;
static unsigned uref = 0; unsigned edif_uref = 0;
static void set_nexus_joint(ivl_nexus_t nex, const char*joint) void edif_set_nexus_joint(ivl_nexus_t nex, const char*joint)
{ {
size_t newlen; size_t newlen;
struct nexus_recall*rec; struct nexus_recall*rec;
@ -91,7 +91,7 @@ static void show_root_ports_edif(ivl_scope_t root)
use_name, dir); use_name, dir);
sprintf(jbuf, "(portRef %s)", use_name); sprintf(jbuf, "(portRef %s)", use_name);
set_nexus_joint(ivl_signal_pin(sig, 0), jbuf); edif_set_nexus_joint(ivl_signal_pin(sig, 0), jbuf);
} else { } else {
unsigned pin; unsigned pin;
@ -101,12 +101,50 @@ static void show_root_ports_edif(ivl_scope_t root)
"\"%s[%u]\") (direction %s))\n", use_name, "\"%s[%u]\") (direction %s))\n", use_name,
pin, use_name, pin, dir); pin, use_name, pin, dir);
sprintf(jbuf, "(portRef %s_%u)", use_name, pin); sprintf(jbuf, "(portRef %s_%u)", use_name, pin);
set_nexus_joint(ivl_signal_pin(sig, pin), jbuf); edif_set_nexus_joint(ivl_signal_pin(sig, pin), jbuf);
} }
} }
} }
} }
void edif_show_header_generic(ivl_design_t des, const char*library)
{
ivl_scope_t root = ivl_design_root(des);
/* write the primitive header */
fprintf(xnf, "(edif %s\n", ivl_scope_name(root));
fprintf(xnf, " (edifVersion 2 0 0)\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (keywordMap (keywordLevel 0))\n");
fprintf(xnf, " (status\n");
fprintf(xnf, " (written\n");
fprintf(xnf, " (timeStamp 0 0 0 0 0 0)\n");
fprintf(xnf, " (author \"unknown\")\n");
fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
/* Write out the external references here? */
fputs(library, xnf);
/* Write out the library header */
fprintf(xnf, " (library DESIGN\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (technology (numberDefinition))\n");
/* The root module is a cell in the library. */
fprintf(xnf, " (cell %s\n", ivl_scope_name(root));
fprintf(xnf, " (cellType GENERIC)\n");
fprintf(xnf, " (view Netlist_representation\n");
fprintf(xnf, " (viewType NETLIST)\n");
fprintf(xnf, " (interface\n");
show_root_ports_edif(root);
fprintf(xnf, " )\n"); /* end the (interface ) sexp */
fprintf(xnf, " (contents\n");
}
static const char*external_library_text = static const char*external_library_text =
" (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n" " (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n"
" (cell AND2 (cellType GENERIC)\n" " (cell AND2 (cellType GENERIC)\n"
@ -156,42 +194,9 @@ static const char*external_library_text =
" )\n" " )\n"
; ;
static void edif_show_header(ivl_design_t des) static void edif_show_header(ivl_design_t des)
{ {
ivl_scope_t root = ivl_design_root(des); edif_show_header_generic(des, external_library_text);
/* write the primitive header */
fprintf(xnf, "(edif %s\n", ivl_scope_name(root));
fprintf(xnf, " (edifVersion 2 0 0)\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (keywordMap (keywordLevel 0))\n");
fprintf(xnf, " (status\n");
fprintf(xnf, " (written\n");
fprintf(xnf, " (timeStamp 0 0 0 0 0 0)\n");
fprintf(xnf, " (author \"unknown\")\n");
fprintf(xnf, " (program \"Icarus Verilog/fpga.tgt\")))\n");
/* Write out the external references here? */
fputs(external_library_text, xnf);
/* Write out the library header */
fprintf(xnf, " (library DESIGN\n");
fprintf(xnf, " (edifLevel 0)\n");
fprintf(xnf, " (technology (numberDefinition))\n");
/* The root module is a cell in the library. */
fprintf(xnf, " (cell %s\n", ivl_scope_name(root));
fprintf(xnf, " (cellType GENERIC)\n");
fprintf(xnf, " (view Netlist_representation\n");
fprintf(xnf, " (viewType NETLIST)\n");
fprintf(xnf, " (interface\n");
show_root_ports_edif(root);
fprintf(xnf, " )\n"); /* end the (interface ) sexp */
fprintf(xnf, " (contents\n");
} }
static void edif_show_consts(ivl_design_t des) static void edif_show_consts(ivl_design_t des)
@ -209,7 +214,7 @@ static void edif_show_consts(ivl_design_t des)
const char*name; const char*name;
const char*port; const char*port;
uref += 1; edif_uref += 1;
switch (val[pin]) { switch (val[pin]) {
case '0': case '0':
@ -229,17 +234,17 @@ static void edif_show_consts(ivl_design_t des)
fprintf(xnf, "(instance U%u " fprintf(xnf, "(instance U%u "
"(viewRef Netlist_representation" "(viewRef Netlist_representation"
" (cellRef %s (libraryRef VIRTEX))))\n", " (cellRef %s (libraryRef VIRTEX))))\n",
uref, name); edif_uref, name);
sprintf(jbuf, "(portRef %s (instanceRef U%u))", sprintf(jbuf, "(portRef %s (instanceRef U%u))",
port, uref); port, edif_uref);
set_nexus_joint(nex, jbuf); edif_set_nexus_joint(nex, jbuf);
} }
} }
} }
static void edif_show_footer(ivl_design_t des) void edif_show_footer(ivl_design_t des)
{ {
unsigned nref = 0; unsigned nref = 0;
struct nexus_recall*cur; struct nexus_recall*cur;
@ -275,7 +280,7 @@ static void edif_show_logic(ivl_net_logic_t net)
char jbuf[1024]; char jbuf[1024];
unsigned idx; unsigned idx;
uref += 1; edif_uref += 1;
switch (ivl_logic_type(net)) { switch (ivl_logic_type(net)) {
@ -284,33 +289,33 @@ static void edif_show_logic(ivl_net_logic_t net)
assert(ivl_logic_pins(net) >= 3); assert(ivl_logic_pins(net) >= 3);
fprintf(xnf, "(instance (rename U%u \"%s\")", fprintf(xnf, "(instance (rename U%u \"%s\")",
uref, ivl_logic_name(net)); edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef Netlist_representation" fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef AND%u (libraryRef VIRTEX))))\n", " (cellRef AND%u (libraryRef VIRTEX))))\n",
ivl_logic_pins(net) - 1); ivl_logic_pins(net) - 1);
sprintf(jbuf, "(portRef O (instanceRef U%u))", uref); sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
set_nexus_joint(ivl_logic_pin(net, 0), jbuf); edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) { for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
sprintf(jbuf, "(portRef I%u (instanceRef U%u))", sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
idx-1, uref); idx-1, edif_uref);
set_nexus_joint(ivl_logic_pin(net, idx), jbuf); edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
} }
break; break;
case IVL_LO_BUF: case IVL_LO_BUF:
assert(ivl_logic_pins(net) == 2); assert(ivl_logic_pins(net) == 2);
fprintf(xnf, "(instance (rename U%u \"%s\")", fprintf(xnf, "(instance (rename U%u \"%s\")",
uref, ivl_logic_name(net)); edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef Netlist_representation" fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef BUF (libraryRef VIRTEX))))\n"); " (cellRef BUF (libraryRef VIRTEX))))\n");
sprintf(jbuf, "(portRef O (instanceRef U%u))", uref); sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
set_nexus_joint(ivl_logic_pin(net, 0), jbuf); edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
sprintf(jbuf, "(portRef I (instanceRef U%u))", uref); sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
set_nexus_joint(ivl_logic_pin(net, 1), jbuf); edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
break; break;
case IVL_LO_NOR: case IVL_LO_NOR:
@ -318,18 +323,18 @@ static void edif_show_logic(ivl_net_logic_t net)
assert(ivl_logic_pins(net) >= 3); assert(ivl_logic_pins(net) >= 3);
fprintf(xnf, "(instance (rename U%u \"%s\")", fprintf(xnf, "(instance (rename U%u \"%s\")",
uref, ivl_logic_name(net)); edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef Netlist_representation" fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef NOR%u (libraryRef VIRTEX))))\n", " (cellRef NOR%u (libraryRef VIRTEX))))\n",
ivl_logic_pins(net) - 1); ivl_logic_pins(net) - 1);
sprintf(jbuf, "(portRef O (instanceRef U%u))", uref); sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
set_nexus_joint(ivl_logic_pin(net, 0), jbuf); edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) { for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
sprintf(jbuf, "(portRef I%u (instanceRef U%u))", sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
idx-1, uref); idx-1, edif_uref);
set_nexus_joint(ivl_logic_pin(net, idx), jbuf); edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
} }
break; break;
@ -338,34 +343,34 @@ static void edif_show_logic(ivl_net_logic_t net)
} }
} }
static void edif_show_dff(ivl_lpm_t net) void edif_show_generic_dff(ivl_lpm_t net)
{ {
ivl_nexus_t nex; ivl_nexus_t nex;
char jbuf[1024]; char jbuf[1024];
assert(ivl_lpm_width(net) == 1); assert(ivl_lpm_width(net) == 1);
uref += 1; edif_uref += 1;
fprintf(xnf, "(instance (rename U%u \"%s\")", uref, ivl_lpm_name(net)); fprintf(xnf, "(instance (rename U%u \"%s\")", edif_uref, ivl_lpm_name(net));
fprintf(xnf, " (viewRef Netlist_representation" fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef FDCE (libraryRef VIRTEX))))\n"); " (cellRef FDCE (libraryRef VIRTEX))))\n");
nex = ivl_lpm_q(net, 0); nex = ivl_lpm_q(net, 0);
sprintf(jbuf, "(portRef Q (instanceRef U%u))", uref); sprintf(jbuf, "(portRef Q (instanceRef U%u))", edif_uref);
set_nexus_joint(nex, jbuf); edif_set_nexus_joint(nex, jbuf);
nex = ivl_lpm_data(net, 0); nex = ivl_lpm_data(net, 0);
sprintf(jbuf, "(portRef D (instanceRef U%u))", uref); sprintf(jbuf, "(portRef D (instanceRef U%u))", edif_uref);
set_nexus_joint(nex, jbuf); edif_set_nexus_joint(nex, jbuf);
nex = ivl_lpm_clk(net); nex = ivl_lpm_clk(net);
sprintf(jbuf, "(portRef C (instanceRef U%u))", uref); sprintf(jbuf, "(portRef C (instanceRef U%u))", edif_uref);
set_nexus_joint(nex, jbuf); edif_set_nexus_joint(nex, jbuf);
if ((nex = ivl_lpm_enable(net))) { if ((nex = ivl_lpm_enable(net))) {
sprintf(jbuf, "(portRef CE (instanceRef U%u))", uref); sprintf(jbuf, "(portRef CE (instanceRef U%u))", edif_uref);
set_nexus_joint(nex, jbuf); edif_set_nexus_joint(nex, jbuf);
} }
} }
@ -374,7 +379,7 @@ const struct device_s d_generic_edif = {
edif_show_header, edif_show_header,
edif_show_footer, edif_show_footer,
edif_show_logic, edif_show_logic,
edif_show_dff, edif_show_generic_dff,
0, 0,
0, 0,
0, 0,
@ -384,6 +389,9 @@ const struct device_s d_generic_edif = {
/* /*
* $Log: d-generic-edif.c,v $ * $Log: d-generic-edif.c,v $
* Revision 1.3 2001/09/06 04:28:40 steve
* Separate the virtex and generic-edif code generators.
*
* Revision 1.2 2001/09/02 23:53:55 steve * Revision 1.2 2001/09/02 23:53:55 steve
* Add virtex support for some basic logic, the DFF * Add virtex support for some basic logic, the DFF
* and constant signals. * and constant signals.

175
tgt-fpga/d-virtex.c Normal file
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@ -0,0 +1,175 @@
/*
* Copyright (c) 2001 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ident "$Id: d-virtex.c,v 1.1 2001/09/06 04:28:40 steve Exp $"
# include "device.h"
# include "fpga_priv.h"
# include <stdlib.h>
# include <string.h>
# include <malloc.h>
# include <assert.h>
/*
* This is the EDIF code generator for VIRTEX style parts. It uses the
* VIRTEX primitives from the unified library.
*/
static const char*virtex_library_text =
" (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n"
" (cell AND2 (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface\n"
" (port O (direction OUTPUT))\n"
" (port I0 (direction INPUT))\n"
" (port I1 (direction INPUT)))))\n"
" (cell BUF (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface\n"
" (port O (direction OUTPUT))\n"
" (port I (direction INPUT)))))\n"
" (cell FDCE (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface\n"
" (port Q (direction OUTPUT))\n"
" (port D (direction INPUT))\n"
" (port C (direction INPUT))\n"
" (port CE (direction INPUT)))))\n"
" (cell GND (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface (port G (direction OUTPUT)))))\n"
" (cell NOR2 (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface\n"
" (port O (direction OUTPUT))\n"
" (port I0 (direction INPUT))\n"
" (port I1 (direction INPUT)))))\n"
" (cell NOR3 (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface\n"
" (port O (direction OUTPUT))\n"
" (port I0 (direction INPUT))\n"
" (port I1 (direction INPUT))\n"
" (port I2 (direction INPUT)))))\n"
" (cell VCC (cellType GENERIC)\n"
" (view Netlist_representation\n"
" (viewType NETLIST)\n"
" (interface (port P (direction OUTPUT)))))\n"
" )\n"
;
static void edif_show_header(ivl_design_t des)
{
edif_show_header_generic(des, virtex_library_text);
}
static void edif_show_logic(ivl_net_logic_t net)
{
char jbuf[1024];
unsigned idx;
edif_uref += 1;
switch (ivl_logic_type(net)) {
case IVL_LO_AND:
assert(ivl_logic_pins(net) <= 10);
assert(ivl_logic_pins(net) >= 3);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef AND%u (libraryRef VIRTEX))))\n",
ivl_logic_pins(net) - 1);
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
idx-1, edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
}
break;
case IVL_LO_BUF:
assert(ivl_logic_pins(net) == 2);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef BUF (libraryRef VIRTEX))))\n");
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
break;
case IVL_LO_NOR:
assert(ivl_logic_pins(net) <= 10);
assert(ivl_logic_pins(net) >= 3);
fprintf(xnf, "(instance (rename U%u \"%s\")",
edif_uref, ivl_logic_name(net));
fprintf(xnf, " (viewRef Netlist_representation"
" (cellRef NOR%u (libraryRef VIRTEX))))\n",
ivl_logic_pins(net) - 1);
sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
idx-1, edif_uref);
edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
}
break;
default:
fprintf(stderr, "UNSUPPORT LOGIC TYPE: %u\n", ivl_logic_type(net));
}
}
const struct device_s d_virtex_edif = {
edif_show_header,
edif_show_footer,
edif_show_logic,
edif_show_generic_dff,
0,
0,
0,
0
};
/*
* $Log: d-virtex.c,v $
* Revision 1.1 2001/09/06 04:28:40 steve
* Separate the virtex and generic-edif code generators.
*
*/

34
tgt-fpga/fpga.txt
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@ -2,16 +2,36 @@
FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
Copyright 2001 Stephen Williams Copyright 2001 Stephen Williams
$Id: fpga.txt,v 1.1 2001/09/02 23:58:49 steve Exp $ $Id: fpga.txt,v 1.2 2001/09/06 04:28:40 steve Exp $
The FPGA code generator supports a variety of FPGA devices, writing
XNF or EDIF depending on the target. You can select the architecture
of the device, and the detailed part name. The architecture is used to
select library primitives, and the detailed part name is written into
the generated file for the use of downstream tools.
INVOKING THE FPGA TARGET INVOKING THE FPGA TARGET
This code generator is invoked with the -tfpga flag to iverilog. The The code generator is invoked with the -tfpga flag to iverilog. It
code generator understands the part= and the arch= parameters, which understands the part= and the arch= parameters, which can be set with
can be set with the -p flag of iverilog: the -p flag of iverilog:
iverilog -parch=virtex -fpart=v50-pq240-6 -tfpga foo.vl iverilog -parch=virtex -fpart=v50-pq240-6 -tfpga foo.vl
This example selects the virtext architecture, and give the detailed
part number as v50-pq240-6. The output is written into a.out unless a
different output file is specified with the -o flag.
The following is a list of architecture types that this code generator
supports.
* arch=generic-edif
This is generic EDIF code. It doesn't necessarily work because the
external library is not available to the code generator. But, what it
does is generate generic style gates that a portability library can
map to target gates if desired.
* arch=generic-xnf * arch=generic-xnf
If this is selected, then the output is formatted as an XNF file, If this is selected, then the output is formatted as an XNF file,
@ -25,7 +45,8 @@ code for your part.
If this is selected, then the output is formatted as an EDIF 200 file, If this is selected, then the output is formatted as an EDIF 200 file,
suitable for Virtex class devices. This is supposed to know that you suitable for Virtex class devices. This is supposed to know that you
are targeting a Virtex part, so can generate primitives instead of are targeting a Virtex part, so can generate primitives instead of
using external macros. using external macros. It includes the VIRTEX internal library, and
should work properly for any Virtex part.
XNF ROOT PORTS XNF ROOT PORTS
@ -65,6 +86,9 @@ definitions, including the proper direction marks.
--- ---
$Log: fpga.txt,v $ $Log: fpga.txt,v $
Revision 1.2 2001/09/06 04:28:40 steve
Separate the virtex and generic-edif code generators.
Revision 1.1 2001/09/02 23:58:49 steve Revision 1.1 2001/09/02 23:58:49 steve
Add documentation for the code generator. Add documentation for the code generator.

41
tgt-fpga/fpga_priv.h
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@ -18,7 +18,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ident "$Id: fpga_priv.h,v 1.3 2001/09/02 21:33:07 steve Exp $" #ident "$Id: fpga_priv.h,v 1.4 2001/09/06 04:28:40 steve Exp $"
# include <stdio.h> # include <stdio.h>
# include "device.h" # include "device.h"
@ -43,8 +43,47 @@ extern void xnf_mangle_lpm_name(ivl_lpm_t net, char*buf, size_t nbuf);
extern const char*xnf_mangle_nexus_name(ivl_nexus_t net); extern const char*xnf_mangle_nexus_name(ivl_nexus_t net);
/*
* These are generic EDIF functions that EDIF targets use.
*
* edif_show_header_generic
* This function draws the header part of the EDIF file, including
* the ports of the module, if there are any. Also include the
* library string where the external library would go.
*
* edif_show_footer
* This completes the net items, draws the constant references, then
* writes out the final declarations of the EDIF file.
*
* edif_set_nexus_joint
* This stores joint information in the nexus, and save the nexus in
* a list the edif_show_footer function later uses that list to draw
* all the join records.
*
* edif_show_generic_dff
* The edif DFF is an FDCE. This function draws an FDCE for the lpm
* DFF of the design.
*
* edif_uref
* This global variable keeps count of the devices drawn. Since the
* EDIF format has very simple names, each device instead has a uref
* and a name of the form U%u. A (rename U% "foo") preserves the
* real name.
*/
extern void edif_show_header_generic(ivl_design_t des, const char*library);
extern void edif_show_footer(ivl_design_t des);
extern void edif_set_nexus_joint(ivl_nexus_t nex, const char*joint);
extern void edif_show_generic_dff(ivl_lpm_t net);
extern unsigned edif_uref;
/* /*
* $Log: fpga_priv.h,v $ * $Log: fpga_priv.h,v $
* Revision 1.4 2001/09/06 04:28:40 steve
* Separate the virtex and generic-edif code generators.
*
* Revision 1.3 2001/09/02 21:33:07 steve * Revision 1.3 2001/09/02 21:33:07 steve
* Rearrange the XNF code generator to be generic-xnf * Rearrange the XNF code generator to be generic-xnf
* so that non-XNF code generation is also possible. * so that non-XNF code generation is also possible.

8
tgt-fpga/tables.c
View File

@ -16,7 +16,7 @@
* along with this program; if not, write to the Free Software * along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#ident "$Id: tables.c,v 1.1 2001/09/02 21:33:07 steve Exp $" #ident "$Id: tables.c,v 1.2 2001/09/06 04:28:40 steve Exp $"
# include "fpga_priv.h" # include "fpga_priv.h"
# include <string.h> # include <string.h>
@ -24,6 +24,7 @@
extern const struct device_s d_generic; extern const struct device_s d_generic;
extern const struct device_s d_generic_edif; extern const struct device_s d_generic_edif;
extern const struct device_s d_virtex_edif;
const struct device_table_s { const struct device_table_s {
@ -32,7 +33,7 @@ const struct device_table_s {
} device_table[] = { } device_table[] = {
{ "generic-edif", &d_generic_edif }, { "generic-edif", &d_generic_edif },
{ "generic-xnf", &d_generic }, { "generic-xnf", &d_generic },
{ "virtex", &d_generic_edif }, { "virtex", &d_virtex_edif },
{ 0, 0 } { 0, 0 }
}; };
@ -53,6 +54,9 @@ device_t device_from_arch(const char*arch)
/* /*
* $Log: tables.c,v $ * $Log: tables.c,v $
* Revision 1.2 2001/09/06 04:28:40 steve
* Separate the virtex and generic-edif code generators.
*
* Revision 1.1 2001/09/02 21:33:07 steve * Revision 1.1 2001/09/02 21:33:07 steve
* Rearrange the XNF code generator to be generic-xnf * Rearrange the XNF code generator to be generic-xnf
* so that non-XNF code generation is also possible. * so that non-XNF code generation is also possible.