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@ -5,7 +5,7 @@ iverilog - Icarus Verilog compiler
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.SH SYNOPSIS
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.SH SYNOPSIS
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.B iverilog
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.B iverilog
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[-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value]
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[-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value]
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[-g1|-g2|-g2x|-gspecify|-gxtypes|-gio-range-error]
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[-dflag=value] [-g1|-g2|-g2x|-gspecify|-gxtypes|-gio-range-error]
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[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
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[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
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[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
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[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
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@ -43,6 +43,12 @@ Verilog source.
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.B -D\fImacro=defn\fP
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.B -D\fImacro=defn\fP
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Defines macro \fImacro\fP as \fIdefn\fP.
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Defines macro \fImacro\fP as \fIdefn\fP.
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.TP 8
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.TP 8
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.B -d\fIname\fP
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Activate a class of compiler debugging messages. The \fB-d\fP switch may
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be used as often as necessary to activate all the desired classes.
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Supported classes are scope, eval_tree, elaborate, and synth2;
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any other names are ignored.
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.TP 8
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.B -E
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.B -E
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Preprocess the Verilog source, but do not compile it. The output file
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Preprocess the Verilog source, but do not compile it. The output file
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is the Verilog input, but with file inclusions and macro references
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is the Verilog input, but with file inclusions and macro references
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