Capitalize Verilog in a few places

(cherry picked from commit 89edf62206)

elab_lval.cc

@@ -290,13 +290,13 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
       }
 
 	// We are processing the tail of a string of names. For
-	// example, the verilog may be "a.b.c", so we are processing
+	// example, the Verilog may be "a.b.c", so we are processing
 	// "c" at this point. (Note that if method_name is not nil,
 	// then this is "a.b.c.method" and "a.b.c" is a struct or class.)
       const name_component_t&name_tail = path_.back();
 
 	// Use the last index to determine what kind of select
-	// (bit/part/etc) we are processing. For example, the verilog
+	// (bit/part/etc) we are processing. For example, the Verilog
 	// may be "a.b.c[1][2][<index>]". All but the last index must
 	// be simple expressions, only the <index> may be a part
 	// select etc., so look at it to determine how we will be

netlist.h

@@ -713,7 +713,7 @@ class NetNet  : public NetObj, public PortType {
 	/* This method returns a reference to the packed dimensions
 	   for the vector. These are arranged as a list where the
 	   first range in the list (front) is the left-most range in
-	   the verilog declaration. These packed dims are compressed
+	   the Verilog declaration. These packed dims are compressed
 	   to represent the dimensions of all the subtypes. */
       const std::vector<netrange_t>& packed_dims() const { return slice_dims_; }
 

netmisc.cc

@@ -925,7 +925,7 @@ NetExpr* elab_and_eval(Design*des, NetScope*scope, PExpr*pe,
 
 /*
  * This variant of elab_and_eval does the expression losslessly, no
- * matter what the generation of verilog. This is in support of
+ * matter what the generation of Verilog. This is in support of
  * certain special contexts, notably index expressions.
  */
 NetExpr* elab_and_eval_lossless(Design*des, NetScope*scope, PExpr*pe,

vpi/sys_icarus.c

@@ -60,7 +60,7 @@ static PLI_INT32 missing_optional_compiletf(ICARUS_VPI_CONST PLI_BYTE8* name)
 {
       vpiHandle callh = vpi_handle(vpiSysTfCall, 0);
 
-      vpi_printf("SORRY: %s:%d: %s() is not available in Icarus verilog.\n",
+      vpi_printf("SORRY: %s:%d: %s() is not available in Icarus Verilog.\n",
                  vpi_get_str(vpiFile, callh), (int)vpi_get(vpiLineNo, callh),
                  name);
       vpi_control(vpiFinish, 1);

vvp/vvp_net_sig.h

@@ -393,7 +393,7 @@ class vvp_fun_signal_object_aa : public vvp_fun_signal_object, public automatic_
 /* vvp_wire
  * The vvp_wire is different from vvp_variable objects in that it
  * exists only as a filter. The vvp_wire class tree is for
- * implementing verilog wires/nets (as opposed to regs/variables).
+ * implementing Verilog wires/nets (as opposed to regs/variables).
  *
  *   vvp_vpi_callback
  *          |