luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Emit VHDL symbols as escaped identifiers

This commit is contained in:
Stephen Williams 2011-08-20 12:11:49 -07:00
parent 78788d17fe
commit a46c66130b
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
vhdlpp/expression_emit.cc
View File

@ -294,7 +294,7 @@ int ExpName::emit(ostream&out, Entity*ent, Architecture*arc)
{ {
int errors = 0; int errors = 0;
out << name_; out << "\\" << name_ << " ";
if (index_) { if (index_) {
out << "["; out << "[";
errors += index_->emit(out, ent, arc); errors += index_->emit(out, ent, arc);

4
vhdlpp/vtype_emit.cc
View File

@ -39,7 +39,7 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
out << "signed "; out << "signed ";
if (msb != lsb) if (msb != lsb)
out << "[" << msb << ":" << lsb << "] "; out << "[" << msb << ":" << lsb << "] ";
out << name; out << "\\" << name << " ";
break; break;
case VType::VBOOL: case VType::VBOOL:
out << wire << " bool "; out << wire << " bool ";
@ -47,7 +47,7 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
out << "signed "; out << "signed ";
if (msb != lsb) if (msb != lsb)
out << "[" << msb << ":" << lsb << "] "; out << "[" << msb << ":" << lsb << "] ";
out << name; out << "\\" << name << " ";
break; break;
} }