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VHDL: Add some missing newlines

This commit is contained in:
Cary R 2015-12-19 10:48:00 -08:00
parent 4b9b0b7125
commit a4177f6ddc
1 changed files with 2 additions and 2 deletions
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4
vhdlpp/parse.y
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@ -669,7 +669,7 @@ component_configuration
block_configuration_opt
K_end K_for ';'
{
sorrymsg(@1, "Component configuration in not yet supported");
sorrymsg(@1, "Component configuration in not yet supported\n");
if($3) delete $3;
delete $2;
}
@ -882,7 +882,7 @@ configuration_declaration
K_end K_configuration_opt identifier_opt ';'
{
if(design_entities.find(lex_strings.make($4)) == design_entities.end())
errormsg(@4, "Couldn't find entity %s used in configuration declaration", $4);
errormsg(@4, "Couldn't find entity %s used in configuration declaration\n", $4);
//choose_architecture_for_entity();
sorrymsg(@1, "Configuration declaration is not yet supported.\n");
}