vec4 cassign to part selects.

tgt-vvp/vvp_process.c

@@ -939,6 +939,7 @@ static void force_vector_to_lval(ivl_statement_t net)
       for (lidx = 0 ;  lidx < ivl_stmt_lvals(net) ; lidx += 1) {
 	    ivl_lval_t lval = ivl_stmt_lval(net, lidx);
 	    ivl_signal_t lsig = ivl_lval_sig(lval);
+	    ivl_expr_t part_off_ex = ivl_lval_part_off(lval);
 
 	    ivl_expr_t word_idx = ivl_lval_idx(lval);
 	    unsigned long use_word = 0;
@@ -964,14 +965,23 @@ static void force_vector_to_lval(ivl_statement_t net)
 		  }
 	    }
 
+
+	    if (lidx+1 < ivl_stmt_lvals(net))
+		  fprintf(vvp_out, "    %%split/vec4 %u;\n", ivl_lval_width(lval));
+
 	      /* L-Value must be a signal: reg or wire */
 	    assert(lsig != 0);
 	      /* Do not support bit or part selects of l-values yet. */
-	    assert(ivl_lval_width(lval) == ivl_signal_width(lsig));
+	    if (part_off_ex) {
-	    assert(!ivl_lval_part_off(lval));
+		  int off_index = allocate_word();
-
+		  draw_eval_expr_into_integer(part_off_ex, off_index);
-
+		  fprintf(vvp_out, "    %s/off v%p_%lu, %d;\n", command_name, lsig, use_word, off_index);
-	    fprintf(vvp_out, "    %s v%p_%lu;\n", command_name, lsig, use_word);
+		  clr_word(off_index);
+	    } else {
+		  assert(ivl_lval_width(lval) == ivl_signal_width(lsig));
+		  assert(!ivl_lval_part_off(lval));
+		  fprintf(vvp_out, "    %s v%p_%lu;\n", command_name, lsig, use_word);
+	    }
 
       }
 }

vvp/codes.h

@@ -64,8 +64,8 @@ extern bool of_BLEND_WR(vthread_t thr, vvp_code_t code);
 extern bool of_BREAKPOINT(vthread_t thr, vvp_code_t code);
 extern bool of_CASSIGN_LINK(vthread_t thr, vvp_code_t code);
 extern bool of_CASSIGN_VEC4(vthread_t thr, vvp_code_t code);
+extern bool of_CASSIGN_VEC4_OFF(vthread_t thr, vvp_code_t code);
 extern bool of_CASSIGN_WR(vthread_t thr, vvp_code_t code);
-extern bool of_CASSIGN_X0(vthread_t thr, vvp_code_t code);
 extern bool of_CAST2(vthread_t thr, vvp_code_t code);
 extern bool of_CMPIS(vthread_t thr, vvp_code_t code);
 extern bool of_CMPIU(vthread_t thr, vvp_code_t code);

vvp/compile.cc

@@ -113,10 +113,10 @@ static const struct opcode_table_s opcode_table[] = {
       { "%blend",    of_BLEND,   0,  {OA_NONE,  OA_NONE,     OA_NONE} },
       { "%blend/wr", of_BLEND_WR,0,  {OA_NONE,  OA_NONE,     OA_NONE} },
       { "%breakpoint", of_BREAKPOINT, 0,  {OA_NONE, OA_NONE, OA_NONE} },
-      { "%cassign/link",of_CASSIGN_LINK,2,{OA_FUNC_PTR,OA_FUNC_PTR2,OA_NONE} },
+      { "%cassign/link",    of_CASSIGN_LINK,    2,{OA_FUNC_PTR,OA_FUNC_PTR2,OA_NONE} },
-      { "%cassign/vec4",of_CASSIGN_VEC4,1,{OA_FUNC_PTR,OA_NONE ,    OA_NONE} },
+      { "%cassign/vec4",    of_CASSIGN_VEC4,    1,{OA_FUNC_PTR,OA_NONE,     OA_NONE} },
+      { "%cassign/vec4/off",of_CASSIGN_VEC4_OFF,2,{OA_FUNC_PTR,OA_BIT1,     OA_NONE} },
       { "%cassign/wr",  of_CASSIGN_WR,  1,{OA_FUNC_PTR,OA_NONE,     OA_NONE} },
-      { "%cassign/x0",of_CASSIGN_X0,3,{OA_FUNC_PTR,OA_BIT1,  OA_BIT2} },
       { "%cast2",  of_CAST2,  3,  {OA_BIT1,     OA_BIT2,     OA_NUMBER} },
       { "%cmp/s",  of_CMPS,   0,  {OA_NONE,     OA_NONE,     OA_NONE} },
       { "%cmp/str",of_CMPSTR, 0,  {OA_NONE,     OA_NONE,     OA_NONE} },

vvp/opcodes.txt

@@ -264,6 +264,7 @@ This may not work on all platforms. If run-time debugging is compiled
 out, then this function is a no-op.
 
 * %cassign/vec4 <var-label>
+* %cassign/vec4/off <var-label>, <off-index>
 
 Perform a continuous assign of a constant value to the target
 variable. This is similar to %set, but it uses the cassign port
@@ -277,14 +278,6 @@ Perform a continuous assign of a constant real value to the target
 variable. See %cassign/v above. The value is popped from the real
 value stack.
 
-* %cassign/x0 <label>, <bit>, <wid>
-
-Perform continuous assign of a constant value to part of the target
-variable. This is similar to %set/x instruction, but it uses the
-cassign port (port-1) of the signal functor instead of the normal
-assign port (port-0), so the signal responds differently. See
-"VARIABLE STATEMENTS" and "NET STATEMENTS" in the README.txt file.
-
 * %cast2 <dst>, <src>, <wid>
 
 Convert the source vector, of type logic, to a bool vector by

vvp/vthread.cc

@@ -1664,6 +1664,42 @@ bool of_CASSIGN_VEC4(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
+/*
+ * %cassign/vec4/off <var>, <off>
+ */
+bool of_CASSIGN_VEC4_OFF(vthread_t thr, vvp_code_t cp)
+{
+      vvp_net_t*net = cp->net;
+      unsigned base_idx = cp->bit_idx[0];
+      long base = thr->words[base_idx].w_int;
+      vvp_vector4_t value = thr->pop_vec4();
+      unsigned wid = value.size();
+
+      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (net->fil);
+      assert(sig);
+
+      if (base < 0 && (wid <= (unsigned)-base))
+	    return true;
+
+      if (base >= (long)sig->value_size())
+	    return true;
+
+      if (base < 0) {
+	    wid -= (unsigned) -base;
+	    base = 0;
+	    value.resize(wid);
+      }
+
+      if (base+wid > sig->value_size()) {
+	    wid = sig->value_size() - base;
+	    value.resize(wid);
+      }
+
+      vvp_net_ptr_t ptr (net, 1);
+      vvp_send_vec4_pv(ptr, value, base, wid, sig->value_size(), 0);
+      return true;
+}
+
 bool of_CASSIGN_WR(vthread_t thr, vvp_code_t cp)
 {
       vvp_net_t*net  = cp->net;
@@ -1676,42 +1712,6 @@ bool of_CASSIGN_WR(vthread_t thr, vvp_code_t cp)
       return true;
 }
 
-bool of_CASSIGN_X0(vthread_t thr, vvp_code_t cp)
-{
-#if 0
-      vvp_net_t*net = cp->net;
-      unsigned base = cp->bit_idx[0];
-      unsigned wid = cp->bit_idx[1];
-
-	// Implicitly, we get the base into the target vector from the
-	// X0 register.
-      long index = thr->words[0].w_int;
-
-      vvp_signal_value*sig = dynamic_cast<vvp_signal_value*> (net->fil);
-
-      if (index < 0 && (wid <= (unsigned)-index))
-	    return true;
-
-      if (index >= (long)sig->value_size())
-	    return true;
-
-      if (index < 0) {
-	    wid -= (unsigned) -index;
-	    index = 0;
-      }
-
-      if (index+wid > sig->value_size())
-	    wid = sig->value_size() - index;
-
-      vvp_vector4_t vector = vthread_bits_to_vector(thr, base, wid);
-
-      vvp_net_ptr_t ptr (net, 1);
-      vvp_send_vec4_pv(ptr, vector, index, wid, sig->value_size(), 0);
-#else
-      fprintf(stderr, "XXXX NOT IMPLEMENTED: %%cassign/x0 ...\n");
-#endif
-      return true;
-}
 
 bool of_CAST2(vthread_t thr, vvp_code_t cp)
 {