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iverilog
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Proper support for XNF synthesis.

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steve 1999-10-09 17:51:23 +00:00
parent 29abc5a69e
commit 9f860e319a
1 changed files with 9 additions and 3 deletions
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12
verilog.sh
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@ -18,6 +18,7 @@
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
# Added support for the -t flag, for odd-ball target types. <steve@icarus.com> # Added support for the -t flag, for odd-ball target types. <steve@icarus.com>
# Added support for functors, especially for the XNF target. <steve@icarus.com>
# Setup variables # Setup variables
execPath=@bindir@ execPath=@bindir@
@ -33,6 +34,8 @@ VPIModulePath=@libdir@/ivl:.
target="vvm" target="vvm"
targetSuffix="" targetSuffix=""
functors=""
flags=""
# If VPI module path aren't set up, warn at least # If VPI module path aren't set up, warn at least
if test -z "${VPI_MODULE_PATH}" ; then if test -z "${VPI_MODULE_PATH}" ; then
@ -41,7 +44,7 @@ if test -z "${VPI_MODULE_PATH}" ; then
fi fi
# Try to extract given parameters # Try to extract given parameters
parameter=`getopt D:I:Xxo:s:t: "$@"` parameter=`getopt D:I:Xxf:o:s:t: "$@"`
eval set -- "${parameter}" eval set -- "${parameter}"
while true ; do while true ; do
@ -49,6 +52,7 @@ while true ; do
-D) extDefines="${extDefines} -D$2" ; shift 2 ;; -D) extDefines="${extDefines} -D$2" ; shift 2 ;;
-I) extIncPath="${extIncPath} -I $2" ; shift 2 ;; -I) extIncPath="${extIncPath} -I $2" ; shift 2 ;;
-X) target="xnf" ; shift ;; -X) target="xnf" ; shift ;;
-f) flags="$flags -f$2" ; shift 2 ;;
-o) outputFile=$2 ; shift 2 ;; -o) outputFile=$2 ; shift 2 ;;
-s) topModule="-s $2 " ; shift 2 ;; -s) topModule="-s $2 " ; shift 2 ;;
-t) target="$2" ; shift 2 ;; -t) target="$2" ; shift 2 ;;
@ -68,9 +72,11 @@ if test -z "${verilogFile}" ; then
exit 1; exit 1;
fi fi
# Shoose a target file suffix based on the target type. # Choose a target file suffix based on the target type.
case "$target" in case "$target" in
vvm) targetSuffix="" ;; vvm) targetSuffix="" ;;
xnf) targetSuffix=".xnf"
functors="-Fxnfsyn -Fsigfold -Fxnfio" ;;
*) targetSuffix=".$target" ;; *) targetSuffix=".$target" ;;
esac esac
@ -92,7 +98,7 @@ fi
# Compile preprocessed verilog file # Compile preprocessed verilog file
${execIVL} -t ${target} -o ${tmpCCFile} ${topModule} ${tmpPPFile} ${execIVL} -t ${target} -o ${tmpCCFile} ${topModule} ${functors} ${flags} ${tmpPPFile}
if test $? -ne 0 ; then if test $? -ne 0 ; then
echo "Verilog compilation failed. Terminating compilation." echo "Verilog compilation failed. Terminating compilation."
rm -f ${tmpCCFile} rm -f ${tmpCCFile}