Stub code for translating expressions

tgt-vhdl/Makefile.in

@@ -49,7 +49,7 @@ dep:
 	$(CXX) $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep
 
-O = vhdl.o vhdl_element.o scope.o process.o stmt.o
+O = vhdl.o vhdl_element.o scope.o process.o stmt.o expr.o
 
 ifeq (@WIN32@,yes)
   TGTLDFLAGS=-L.. -livl

tgt-vhdl/expr.cc

@@ -0,0 +1,33 @@
+/*
+ *  VHDL code generation for expressions.
+ *
+ *  Copyright (C) 2008  Nick Gasson (nick@nickg.me.uk)
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "vhdl_target.h"
+
+#include <iostream>
+#include <cassert>
+
+
+/*
+ * Generate a VHDL expression from a Verilog expression.
+ */
+vhdl_expr *translate_expr(ivl_expr_t e)
+{
+   assert(false);
+}

tgt-vhdl/vhdl_target.h

@@ -14,6 +14,8 @@ int draw_scope(ivl_scope_t scope, void *_parent);
 int draw_process(ivl_process_t net, void *cd);
 int draw_stmt(vhdl_process *proc, ivl_statement_t stmt);
 
+vhdl_expr *translate_expr(ivl_expr_t e);
+
 void remember_entity(vhdl_entity *ent);
 vhdl_entity *find_entity(const std::string &tname);