Generate the jedec to configure the macrocells.

tgt-pal/Makefile.in

@@ -16,7 +16,7 @@
 #    59 Temple Place - Suite 330
 #    Boston, MA 02111-1307, USA
 #
-#ident "$Id: Makefile.in,v 1.4 2000/12/14 23:37:47 steve Exp $"
+#ident "$Id: Makefile.in,v 1.5 2001/01/09 03:10:48 steve Exp $"
 #
 #
 SHELL = /bin/sh
@@ -50,7 +50,7 @@ all: pal.tgt
 	$(CC) -Wall $(CPPFLAGS) -I$(srcdir)/.. -MD -c $< -o $*.o
 	mv $*.d dep
 
-O = imain.o dump_final.o enables.o fit_log.o fit_reg.o pads.o
+O = imain.o dump_final.o emit_jed.o enables.o fit_log.o fit_reg.o pads.o
 
 ifeq (@CYGWIN@,yes)
   TGTLDFLAGS=-L.. -livl

tgt-pal/emit_jed.c

@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
+ *
+ *    This source code is free software; you can redistribute it
+ *    and/or modify it in source code form under the terms of the GNU
+ *    General Public License as published by the Free Software
+ *    Foundation; either version 2 of the License, or (at your option)
+ *    any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+#if !defined(WINNT) && !defined(macintosh)
+#ident "$Id: emit_jed.c,v 1.1 2001/01/09 03:10:48 steve Exp $"
+#endif
+
+# include  "priv.h"
+# include  <stdio.h>
+# include  <malloc.h>
+# include  <assert.h>
+
+static void draw_macrocell_modes(FILE*jfd)
+{
+      unsigned idx;
+      unsigned cfuses;
+      unsigned mode, mcnt;
+
+      for (idx = 0 ;  idx < pins ;  idx += 1) {
+	    char*str;
+	    unsigned ffirst, flast, tmp;
+	    struct pal_bind_s*cur = bind_pin + idx;
+	    if (cur->sop == 0)
+		  continue;
+
+	    cfuses = pal_sop_cfuses(cur->sop);
+	    mcnt = 1 << pal_sop_cfuses(cur->sop);
+	    mode = 0;
+	    for (mode = 0 ;  mode < mcnt ;  mode += 1) {
+
+		  pal_sop_set_mode(cur->sop, mode);
+		  if (cur->reg && !pal_sop_is_register(cur->sop))
+			continue;
+
+		  if (!cur->reg && pal_sop_is_register(cur->sop))
+			continue;
+
+		  if (cur->sop_inv && !pal_sop_is_invert(cur->sop))
+			continue;
+
+		  if (!cur->sop_inv && pal_sop_is_invert(cur->sop))
+			continue;
+
+		  break;
+	    }
+
+	    assert(mode < mcnt);
+
+	    ffirst = pal_sop_cfuse(cur->sop, 0);
+	    flast  = pal_sop_cfuse(cur->sop, 0);
+	    for (tmp = 1 ;  tmp < cfuses ;  tmp += 1) {
+		  unsigned f = pal_sop_cfuse(cur->sop, tmp);
+		  if (f < ffirst)
+			ffirst = f;
+		  if (f > flast)
+			flast = f;
+	    }
+	    assert(flast == (ffirst + cfuses - 1));
+
+	    str = malloc(cfuses+1);
+	    str[cfuses] = 0;
+	    for (tmp = 0 ;  tmp < cfuses ;  tmp += 1) {
+		  if (mode & (1 << (cfuses-tmp-1)))
+			str[pal_sop_cfuse(cur->sop, tmp)-ffirst] = '1';
+		  else
+			str[pal_sop_cfuse(cur->sop, tmp)-ffirst] = '0';
+	    }
+
+
+	    fprintf(jfd, "L%05u %s* Note: ", ffirst, str);
+	    if (cur->nexus)
+		  fprintf(jfd, "%s ", ivl_nexus_name(cur->nexus));
+
+	    { int pin = pal_sop_pin(cur->sop);
+	      if (pin > 0)
+		    fprintf(jfd, "pin %d: ", pin);
+	    }
+	    if (pal_sop_is_register(cur->sop))
+		  fprintf(jfd, "<registered");
+	    else
+		  fprintf(jfd, "<unregistered");
+
+	    if (pal_sop_is_invert(cur->sop))
+		  fprintf(jfd, ", invert");
+
+	    fprintf(jfd, "> *\n");
+
+	    free(str);
+      }
+}
+
+int emit_jedec(const char*path)
+{
+      FILE*jfd;
+
+      jfd = fopen(path, "w");
+      if (jfd == 0) {
+	    fprintf(stderr, "unable to open ``%s'' for output.\n", path);
+	    return -1;
+      }
+
+      fprintf(jfd, "This file created by Icarus Verilog/PAL target\n");
+      fprintf(jfd, "\n\002*\n");
+
+      fprintf(jfd, "QF%u*  Number of fuses*\n", pal_fuses(pal));
+      fprintf(jfd, "F0*  Note: Default fuse set to 0*\n");
+      fprintf(jfd, "G0*  Note: Security fuse NOT blown.*\n");
+
+      draw_macrocell_modes(jfd);
+
+      fclose(jfd);
+      return 0;
+}
+
+/*
+ * $Log: emit_jed.c,v $
+ * Revision 1.1  2001/01/09 03:10:48  steve
+ *  Generate the jedec to configure the macrocells.
+ *
+ */
+

tgt-pal/imain.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: imain.c,v 1.4 2000/12/14 23:37:47 steve Exp $"
+#ident "$Id: imain.c,v 1.5 2001/01/09 03:10:48 steve Exp $"
 #endif
 
 /*
@@ -67,7 +67,7 @@ int target_design(ivl_design_t des)
 	   key. Given the part type, try to open the pal description
 	   so that we can figure out the device. */
       part = ivl_design_flag(des, "part");
-      if (part == 0) {
+      if ((part == 0) || (*part == 0)) {
 	    fprintf(stderr, "error: part must be specified. Specify a\n");
 	    fprintf(stderr, "     : type with the -fpart=<type> option.\n");
 	    return -1;
@@ -89,7 +89,8 @@ int target_design(ivl_design_t des)
       assert(bind_pin);
 
 	/* Connect all the macrocells that drive pins to the pin that
-	   they drive. */
+	   they drive. This doesn't yet look at the design, but is
+	   initializing the bind_pin array with part information. */
       for (idx = 0 ;  idx < pal_sops(pal) ;  idx += 1) {
 	    pal_sop_t sop = pal_sop(pal, idx);
 	    int spin = pal_sop_pin(sop);
@@ -136,6 +137,7 @@ int target_design(ivl_design_t des)
       }
 
       dump_final_design(stdout);
+      emit_jedec(ivl_design_flag(des, "-o"));
 
       pal_free(pal);
       return 0;
@@ -148,6 +150,9 @@ DECLARE_CYGWIN_DLL(DllMain);
 
 /*
  * $Log: imain.c,v $
+ * Revision 1.5  2001/01/09 03:10:48  steve
+ *  Generate the jedec to configure the macrocells.
+ *
  * Revision 1.4  2000/12/14 23:37:47  steve
  *  Start support for fitting the logic.
  *

tgt-pal/priv.h

@@ -19,12 +19,13 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT)
-#ident "$Id: priv.h,v 1.3 2000/12/14 23:37:47 steve Exp $"
+#ident "$Id: priv.h,v 1.4 2001/01/09 03:10:48 steve Exp $"
 #endif
 
 # include  <ivl_target.h>
 # include  <ipal.h>
 
+
 extern pal_t pal;
 
 extern unsigned error_count;
@@ -46,24 +47,49 @@ typedef struct term_s {
       ivl_nexus_t nex;
 } term_t;
 
+/*
+ * This structure describes a target device pin. If the pin is not
+ * controlled by the pal (i.e. it is a power pin) then the sop field
+ * is null. Otherwise, the sop in the macrocell that controls the pin.
+ *
+ * If the pin has an enable, then the sop for the enable function is
+ * stored here as well.
+ *
+ * This structure for collecting the PAL design assumes that all the
+ * macrocells are associated with pins, or are enables for other
+ * pins.
+ *
+ * The bind_pin array is the complete description of the target as it
+ * is accumulated.
+ */
 struct pal_bind_s {
 	/* This is the netlist connection for the pin. */
       ivl_nexus_t nexus;
 	/* If the pin is an output, this is is sop that drives it. */
       pal_sop_t sop;
-	/* If the output has an enable, this is it. */
+
+	/* If the output has an enable, this is it, along with the
+	   single term that activates it. */
       ivl_net_logic_t enable;
       term_t **enable_ex;
+
 	/* If there is a register here, this is it. */
       ivl_lpm_ff_t reg;
       unsigned reg_q;
+
 	/* The input to the cell is this expression. */
       term_t **sop_ex;
+	/* These are the SOP flags that I believe I need. */
+      unsigned sop_inv  : 1;
 };
 
 extern unsigned pins;
 extern struct pal_bind_s* bind_pin;
 
+
+/*
+ * These are various stepps in the fitting process.
+ */
 extern int get_pad_bindings(ivl_scope_t net);
 
 extern void absorb_pad_enables(void);
@@ -72,8 +98,13 @@ extern int fit_registers(ivl_scope_t scope);
 
 extern int fit_logic(void);
 
+extern int emit_jedec(const char*path);
+
 /*
  * $Log: priv.h,v $
+ * Revision 1.4  2001/01/09 03:10:48  steve
+ *  Generate the jedec to configure the macrocells.
+ *
  * Revision 1.3  2000/12/14 23:37:47  steve
  *  Start support for fitting the logic.
  *