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Update to 0.4 release.

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steve 2001-02-04 00:03:57 +00:00
parent 0175c727ee
commit 9e624ac833
1 changed files with 3 additions and 3 deletions
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verilog.spec
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@ -1,7 +1,7 @@
Summary: Icarus Verilog Summary: Icarus Verilog
Name: verilog Name: verilog
Version: 0.4 Version: 0.4
Release: x Release: 1
Copyright: GPL Copyright: GPL
Group: Applications/Engineering Group: Applications/Engineering
Source: ftp://icarus.com/pub/eda/verilog/v0.4/verilog-0.4.tar.gz Source: ftp://icarus.com/pub/eda/verilog/v0.4/verilog-0.4.tar.gz
@ -16,8 +16,8 @@ Provides: iverilog
%description %description
Icarus Verilog is a Verilog compiler that generates a variety of Icarus Verilog is a Verilog compiler that generates a variety of
engineering formats, including a C++ simulation. It strives to be engineering formats, including simulation. It strives to be true
true to the IEEE-1364 standard. to the IEEE-1364 standard.
%prep %prep
%setup -n verilog-0.4 %setup -n verilog-0.4