mirror of
https://github.com/steveicarus/iverilog.git
synced 2026-08-22 13:57:18 +02:00
vvp: Corrected vvp_net_fun_t::recv_vec4_pv() (commit de968e18)
This commit is contained in:
@@ -208,6 +208,15 @@ void vvp_fun_part_pv::recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
|
|||||||
port.ptr()->send_vec4_pv(bit, base_, wid_, vwid_, context);
|
port.ptr()->send_vec4_pv(bit, base_, wid_, vwid_, context);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void vvp_fun_part_pv::recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
|
||||||
|
unsigned base, unsigned wid, unsigned vwid,
|
||||||
|
vvp_context_t ctx)
|
||||||
|
{
|
||||||
|
assert(port.port() == 0);
|
||||||
|
|
||||||
|
port.ptr()->send_vec4_pv(bit, base, wid, vwid, ctx);
|
||||||
|
}
|
||||||
|
|
||||||
void vvp_fun_part_pv::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
|
void vvp_fun_part_pv::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
|
||||||
{
|
{
|
||||||
assert(port.port() == 0);
|
assert(port.port() == 0);
|
||||||
|
|||||||
@@ -109,6 +109,10 @@ class vvp_fun_part_pv : public vvp_net_fun_t {
|
|||||||
void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
|
void recv_vec4(vvp_net_ptr_t port, const vvp_vector4_t&bit,
|
||||||
vvp_context_t context);
|
vvp_context_t context);
|
||||||
|
|
||||||
|
void recv_vec4_pv(vvp_net_ptr_t port, const vvp_vector4_t&bit,
|
||||||
|
unsigned, unsigned, unsigned,
|
||||||
|
vvp_context_t);
|
||||||
|
|
||||||
void recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit);
|
void recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
|
|||||||
+6
-3
@@ -3249,11 +3249,14 @@ void vvp_net_fun_t::recv_vec4(vvp_net_ptr_t, const vvp_vector4_t&,
|
|||||||
assert(0);
|
assert(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void vvp_net_fun_t::recv_vec4_pv(vvp_net_ptr_t ptr, const vvp_vector4_t&bit,
|
void vvp_net_fun_t::recv_vec4_pv(vvp_net_ptr_t, const vvp_vector4_t&bit,
|
||||||
unsigned base, unsigned wid, unsigned vwid,
|
unsigned base, unsigned wid, unsigned vwid,
|
||||||
vvp_context_t ctx)
|
vvp_context_t)
|
||||||
{
|
{
|
||||||
ptr.ptr()->send_vec4_pv(bit, base, wid, vwid, ctx);
|
cerr << "internal error: " << typeid(*this).name() << ": "
|
||||||
|
<< "recv_vec4_pv(" << bit << ", " << base
|
||||||
|
<< ", " << wid << ", " << vwid << ") not implemented" << endl;
|
||||||
|
assert(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
void vvp_net_fun_t::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
|
void vvp_net_fun_t::recv_vec8(vvp_net_ptr_t port, const vvp_vector8_t&bit)
|
||||||
|
|||||||
Reference in New Issue
Block a user