Add a net node for casting to IVL_VT_BOOL values.

BOOL values have a specific cast from LOGIC, this node takes care
of it. Also arrange for the elaboration to insert them in the right
planes and for the code generator to generate them.

expr_synth.cc

@@ -993,7 +993,7 @@ NetNet* NetECast::synthesize(Design*des, NetScope*scope, NetExpr*root)
 
       switch (op()) {
 	  case 'i':
-	    isig = cast_to_int(des, scope, isig, isig->vector_width());
+	    isig = cast_to_int4(des, scope, isig, isig->vector_width());
 	    break;
 	  case 'r':
 	    isig = cast_to_real(des, scope, isig);