Extend VPI and build to for SIMetrix cosimulation

Added: basic vpiPort VPI Objects for vpiModulkes
    vpiDirection, vpiPortIndex,   vpiName, vpiSize attributes

   Since ports do not exist as net-like entities (nets either side
   module instance boundaries are in effect connect directly in
   the language front-ends internal representation) the port information
   is effectively just meta-data passed through t-dll  interface and
   output as a additional annotation of module scopes in vvp.

Added: vpiLocalParam attribute for vpiParameter VPI objects

Added: support build for 32-bit target on 64-bit host (--with-m32
   option to configure.in and minor tweaks to Makefiles and systemc-vpi).

Module.cc

@@ -90,6 +90,22 @@ unsigned Module::find_port(const char*name) const
       return ports.size();
 }
 
+perm_string Module::get_port_name(unsigned idx) const
+{
+
+      assert(idx < ports.size());
+      if (ports[idx] == 0) {
+              /* It is possible to have undeclared ports. These
+                 are ports that are skipped in the declaration,
+                 for example like so: module foo(x ,, y); The
+                 port between x and y is unnamed and thus
+                 inaccessible to binding by name. */
+            return perm_string::literal("");
+      }
+      return ports[idx]->name;
+}
+
+
 
 PGate* Module::get_gate(perm_string name)
 {