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V0.8: Remove more space issues.

This commit is contained in:
Cary R 2011-03-07 10:52:29 -08:00 committed by Stephen Williams
parent ec0c4343e8
commit 9aa80965bd
22 changed files with 120 additions and 120 deletions
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14
driver/main.c
View File

@ -594,10 +594,10 @@ int main(int argc, char **argv)
base=optarg;
}
break;
case 'c':
case 'c':
command_filename = malloc(strlen(optarg)+1);
strcpy(command_filename, optarg);
break;
strcpy(command_filename, optarg);
break;
case 'D':
process_define(optarg);
break;
@ -615,9 +615,9 @@ int main(int argc, char **argv)
if (rc != 0)
return -1;
break;
case 'h':
fprintf(stderr, "%s\n", HELP);
return 1;
case 'h':
fprintf(stderr, "%s\n", HELP);
return 1;
case 'I':
process_include_dir(optarg);
@ -741,7 +741,7 @@ int main(int argc, char **argv)
if (source_count == 0) {
fprintf(stderr, "%s: No input files.\n", argv[0]);
fprintf(stderr, "%s\n", HELP);
fprintf(stderr, "%s\n", HELP);
return 1;
}

126
examples/des.v
View File

@ -162,11 +162,11 @@ end
endmodule
module des(pt, key, ct, clk);
input [1:64] pt;
input [1:64] key;
output [1:64] ct;
input clk;
wire [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
input [1:64] pt;
input [1:64] key;
output [1:64] ct;
input clk;
wire [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire [1:32] l0x,l1x,l2x,l3x,l4x,l5x,l6x,l7x,l8x,l9x,l10x,l11x,l12x,l13x,l14x,l15x,l16x;
wire [1:32] r0x,r1x,r2x,r3x,r4x,r5x,r6x,r7x,r8x,r9x,r10x,r11x,r12x,r13x,r14x,r15x,r16x;
@ -194,9 +194,9 @@ endmodule
module pc1(key, c0x, d0x);
input [1:64] key;
output [1:28] c0x, d0x;
wire [1:56] XX;
input [1:64] key;
output [1:28] c0x, d0x;
wire [1:56] XX;
assign XX[1]=key[57]; assign XX[2]=key[49]; assign XX[3]=key[41]; assign XX[4]=key[33]; assign XX[5]=key[25]; assign XX[6]=key[17]; assign XX[7]=key[9];
assign XX[8]=key[1]; assign XX[9]=key[58]; assign XX[10]=key[50]; assign XX[11]=key[42]; assign XX[12]=key[34]; assign XX[13]=key[26]; assign XX[14]=key[18];
@ -213,9 +213,9 @@ endmodule
module pc2(c,d,k);
input [1:28] c,d;
output [1:48] k;
wire [1:56] YY;
input [1:28] c,d;
output [1:48] k;
wire [1:56] YY;
assign YY[1:28]=c; assign YY[29:56]=d;
@ -231,7 +231,7 @@ endmodule
module rol1(o, i);
output [1:28] o;
output [1:28] o;
input [1:28] i;
assign o={i[2:28],i[1]};
@ -240,7 +240,7 @@ endmodule
module rol2(o, i);
output [1:28] o;
output [1:28] o;
input [1:28] i;
assign o={i[3:28],i[1:2]};
@ -248,10 +248,10 @@ endmodule
module keysched(key,k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x);
input [1:64] key;
output [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire [1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x;
wire [1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x;
input [1:64] key;
output [1:48] k1x,k2x,k3x,k4x,k5x,k6x,k7x,k8x,k9x,k10x,k11x,k12x,k13x,k14x,k15x,k16x;
wire [1:28] c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,c11x,c12x,c13x,c14x,c15x,c16x;
wire [1:28] d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,d11x,d12x,d13x,d14x,d15x,d16x;
pc1 pc1(key, c0x, d0x);
@ -294,10 +294,10 @@ endmodule
module s1(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -370,10 +370,10 @@ endmodule
module s2(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -446,10 +446,10 @@ endmodule
module s3(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -522,10 +522,10 @@ endmodule
module s4(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -598,10 +598,10 @@ endmodule
module s5(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -674,10 +674,10 @@ endmodule
module s6(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -750,10 +750,10 @@ endmodule
module s7(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -826,10 +826,10 @@ endmodule
module s8(clk, b, so);
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
input clk;
input [1:6] b;
output [1:4] so;
reg [1:4] so;
always @(posedge clk)
casex(b)
@ -902,8 +902,8 @@ endmodule
module ip(pt, l0x, r0x);
input [1:64] pt;
output [1:32] l0x, r0x;
input [1:64] pt;
output [1:32] l0x, r0x;
assign l0x[1]=pt[58]; assign l0x[2]=pt[50]; assign l0x[3]=pt[42]; assign l0x[4]=pt[34];
assign l0x[5]=pt[26]; assign l0x[6]=pt[18]; assign l0x[7]=pt[10]; assign l0x[8]=pt[2];
@ -941,10 +941,10 @@ endmodule
module desxor1(e,b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x,k);
input [1:48] e;
output [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
input [1:48] k;
wire [1:48] XX;
input [1:48] e;
output [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
input [1:48] k;
wire [1:48] XX;
assign XX = k ^ e;
assign b1x = XX[1:6];
@ -960,9 +960,9 @@ endmodule
module pp(so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x,ppo);
input [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
output [1:32] ppo;
wire [1:32] XX;
input [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
output [1:32] ppo;
wire [1:32] XX;
assign XX[1:4]=so1x; assign XX[5:8]=so2x; assign XX[9:12]=so3x; assign XX[13:16]=so4x;
assign XX[17:20]=so5x; assign XX[21:24]=so6x; assign XX[25:28]=so7x; assign XX[29:32]=so8x;
@ -980,8 +980,8 @@ endmodule
module desxor2(d,l,q);
input [1:32] d,l;
output [1:32] q;
input [1:32] d,l;
output [1:32] q;
assign q = d ^ l;
@ -994,10 +994,10 @@ input [1:32] li, ri;
input [1:48] k;
output [1:32] lo, ro;
wire [1:48] e;
wire [1:48] e;
wire [1:6] b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x;
wire [1:4] so1x,so2x,so3x,so4x,so5x,so6x,so7x,so8x;
wire [1:32] ppo;
wire [1:32] ppo;
xp xp(ri, e);
desxor1 desxor1(e, b1x, b2x, b3x, b4x, b5x, b6x, b7x, b8x, k);
@ -1018,7 +1018,7 @@ endmodule
module fp(l,r,ct);
input [1:32] l,r;
input [1:32] l,r;
output [1:64] ct;
assign ct[1]=r[8]; assign ct[2]=l[8]; assign ct[3]=r[16]; assign ct[4]=l[16]; assign ct[5]=r[24]; assign ct[6]=l[24]; assign ct[7]=r[32]; assign ct[8]=l[32];

8
examples/pal_reg.v
View File

@ -55,12 +55,12 @@
module register (out, val, clk, oe);
output [7:0] out;
input [7:0] val;
input clk, oe;
input [7:0] val;
input clk, oe;
reg [7:0] Q;
reg [7:0] Q;
wire [7:0] out;
wire [7:0] out;
bufif0 drv[7:0](out, Q, oe);

4
examples/sqrt-virtex.v
View File

@ -252,7 +252,7 @@ endmodule // sqrt32
module main;
reg [31:0] x;
reg clk, reset;
reg clk, reset;
wire [15:0] y;
wire rdy;
@ -354,7 +354,7 @@ module chip_root(clk, rdy, reset, x, y);
input [31:0] x;
output [15:0] y;
wire clk_int;
wire clk_int;
(* cellref="BUFG:O,I" *)
buf gbuf (clk_int, clk);

2
libveriuser/a_object_of_type.c
View File

@ -32,7 +32,7 @@ int acc_object_of_type(handle object, PLI_INT32 type)
if (pli_trace) {
fprintf(pli_trace, "acc_object_of_type(%p \"%s\", %d)",
object, vpi_get_str(vpiName, object), type);
object, vpi_get_str(vpiName, object), type);
fflush(pli_trace);
}

2
libveriuser/mkinstalldirs
View File

@ -27,7 +27,7 @@ do
mkdir "$pathcomp" || lasterr=$?
if test ! -d "$pathcomp"; then
errstatus=$lasterr
errstatus=$lasterr
fi
fi

2
mkinstalldirs
View File

@ -27,7 +27,7 @@ do
mkdir "$pathcomp" || lasterr=$?
if test ! -d "$pathcomp"; then
errstatus=$lasterr
errstatus=$lasterr
fi
fi

4
synth2.cc
View File

@ -34,9 +34,9 @@ static int debug_synth2=0;
#ifdef __FUNCTION__
#define DEBUG_SYNTH2_ENTRY(class) if (debug_synth2) { cerr << "Enter " << class << "::" \
<< __FUNCTION__ << endl; dump(cerr, 4); }
<< __FUNCTION__ << endl; dump(cerr, 4); }
#define DEBUG_SYNTH2_EXIT(class,val) if (debug_synth2) { cerr << "Exit " << class << "::" \
<< __FUNCTION__ << ", result " << val << endl; }
<< __FUNCTION__ << ", result " << val << endl; }
#else
#define DEBUG_SYNTH2_ENTRY(class)

2
verilog.spec
View File

@ -10,7 +10,7 @@ Packager: Stephen Williams <steve@icarus.com>
BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root
BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, termcap
BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, termcap
BuildRequires: libbz2-devel, bzip2, readline-devel
%ifarch x86_64
BuildRequires: glibc-devel-32bit, libbz2-1-32bit, zlib-devel-32bit, glibc-32bit

4
vpi/sys_lxt.c
View File

@ -242,7 +242,7 @@ static PLI_INT32 variable_cb_1(p_cb_data cause)
struct t_cb_data cb;
struct vcd_info*info = (struct vcd_info*)cause->user_data;
if (dump_is_off) return 0;
if (dump_is_off) return 0;
if (dump_header_pending()) return 0;
if (info->scheduled) return 0;
@ -662,7 +662,7 @@ static int draw_scope(vpiHandle item)
case vpiTask: type = "task"; break;
case vpiFunction: type = "function"; break;
case vpiNamedFork: type = "fork"; break;
default: type = "module"; break;
default: type = "module"; break;
}
push_scope(name); /* keep in type info determination for possible future usage */

4
vpi/sys_lxt2.c
View File

@ -244,7 +244,7 @@ static PLI_INT32 variable_cb_1(p_cb_data cause)
struct t_cb_data cb;
struct vcd_info*info = (struct vcd_info*)cause->user_data;
if (dump_is_off) return 0;
if (dump_is_off) return 0;
if (dump_header_pending()) return 0;
if (info->scheduled) return 0;
@ -680,7 +680,7 @@ static int draw_scope(vpiHandle item)
case vpiTask: type = "task"; break;
case vpiFunction: type = "function"; break;
case vpiNamedFork: type = "fork"; break;
default: type = "module"; break;
default: type = "module"; break;
}
push_scope(name); /* keep in type info determination for possible future usage */

4
vpi/sys_vcd.c
View File

@ -196,7 +196,7 @@ static PLI_INT32 variable_cb_1(p_cb_data cause)
struct t_cb_data cb;
struct vcd_info*info = (struct vcd_info*)cause->user_data;
if (dump_is_off) return 0;
if (dump_is_off) return 0;
if (dump_header_pending()) return 0;
if (info->scheduled) return 0;
@ -658,7 +658,7 @@ static int draw_scope(vpiHandle item)
case vpiTask: type = "task"; break;
case vpiFunction: type = "function"; break;
case vpiNamedFork: type = "fork"; break;
default: type = "module"; break;
default: type = "module"; break;
}
fprintf(dump_file, "$scope %s %s $end\n", type, name);

2
vpip/mkinstalldirs
View File

@ -27,7 +27,7 @@ do
mkdir "$pathcomp" || lasterr=$?
if test ! -d "$pathcomp"; then
errstatus=$lasterr
errstatus=$lasterr
fi
fi

4
vvp/compile.cc
View File

@ -63,7 +63,7 @@ enum operand_e {
OA_CODE_PTR,
/* The operand is a variable or net pointer */
OA_FUNC_PTR,
/* The operand is a second functor pointer */
/* The operand is a second functor pointer */
OA_FUNC_PTR2,
/* The operand is a pointer to a memory */
OA_MEM_PTR,
@ -1365,7 +1365,7 @@ void compile_code(char*label, char*mnem, comp_operands_t opa)
code->number = opa->argv[idx].numb;
break;
case OA_MEM_PTR:
case OA_MEM_PTR:
if (opa->argv[idx].ltype != L_SYMB) {
yyerror("operand format");
break;

2
vvp/examples/vector.vvp
View File

@ -2,6 +2,6 @@
main .scope "main";
T0 %vpi_call "$display", "Display the number: %b", 5'b0zx1;
T0 %vpi_call "$display", "Display the number: %b", 5'b0zx1;
%end;
.thread T0;

2
vvp/lexor.lex
View File

@ -119,7 +119,7 @@
".udp" { return K_UDP; }
".udp/c"(omb)? { return K_UDP_C; }
".udp/s"(equ)? { return K_UDP_S; }
".mem" { return K_MEM; }
".mem" { return K_MEM; }
".mem/p"(ort)? { return K_MEM_P; }
".mem/i"(nit)? { return K_MEM_I; }
".force" { return K_FORCE; }

2
vvp/mkinstalldirs
View File

@ -27,7 +27,7 @@ do
mkdir "$pathcomp" || lasterr=$?
if test ! -d "$pathcomp"; then
errstatus=$lasterr
errstatus=$lasterr
fi
fi

4
vvp/stop.cc
View File

@ -456,7 +456,7 @@ void stop_handler(int rc)
printf("** VVP Stop(%d) **\n", rc);
printf("** Current simulation time is %" TIME_FMT "u ticks.\n",
schedule_simtime());
schedule_simtime());
interact_flag = true;
while (interact_flag) {
@ -489,7 +489,7 @@ void stop_handler(int rc)
{
printf("** VVP Stop(%d) **\n", rc);
printf("** Current simulation time is %" TIME_FMT "u ticks.\n",
schedule_simtime());
schedule_simtime());
printf("** Interactive mode not supported, exiting simulation.\n");
exit(0);

2
vvp/vpi_memory.cc
View File

@ -467,7 +467,7 @@ static void memory_word_get_value(vpiHandle ref, s_vpi_value*vp)
break;
}
case vpiIntVal:
case vpiIntVal:
assert(width <= 8 * sizeof vp->value.integer);
vp->value.integer = 0;

40
vvp/vpi_priv.cc
View File

@ -279,7 +279,7 @@ int vpip_time_units_from_handle(vpiHandle obj)
case vpiNet:
case vpiReg:
signal = (struct __vpiSignal*)obj;
return signal->scope->time_units;
return signal->scope->time_units;
default:
fprintf(stderr, "ERROR: vpi_get_time called with object "
@ -429,40 +429,40 @@ vpiHandle vpi_put_value(vpiHandle obj, s_vpi_value*vp,
if (flags != vpiNoDelay) {
vvp_time64_t dly;
switch (when->type) {
case vpiScaledRealTime:
dly = (vvp_time64_t)(when->real *
switch (when->type) {
case vpiScaledRealTime:
dly = (vvp_time64_t)(when->real *
(pow(10,
vpip_time_units_from_handle(obj) -
vpip_get_time_precision())));
break;
case vpiSimTime:
break;
case vpiSimTime:
dly = vpip_timestruct_to_time(when);
break;
default:
break;
default:
dly = 0;
break;
}
}
vpip_put_value_event*put = new vpip_put_value_event;
put->handle = obj;
put->value = *vp;
switch (put->value.format) {
switch (put->value.format) {
/* If this is scheduled make a copy of the string. */
case vpiBinStrVal:
case vpiOctStrVal:
case vpiDecStrVal:
case vpiHexStrVal:
case vpiStringVal:
case vpiBinStrVal:
case vpiOctStrVal:
case vpiDecStrVal:
case vpiHexStrVal:
case vpiStringVal:
put->value.value.str = strdup(put->value.value.str);
break;
/* Do these also need to be copied? */
case vpiTimeVal:
case vpiVectorVal:
case vpiStrengthVal:
default:
case vpiTimeVal:
case vpiVectorVal:
case vpiStrengthVal:
default:
break;
}
}
put->run = &vpip_put_value_callback;
schedule_generic(put, 0, dly, false);
return 0;

2
vvp/vpi_scope.cc
View File

@ -160,7 +160,7 @@ static int compare_types(int code, int type)
(type == vpiIntegerVar ||
type == vpiTimeVar ||
type == vpiRealVar))
return 1;
return 1;
return 0;
}

4
vvp/vpip_to_dec.cc
View File

@ -146,7 +146,7 @@ unsigned vpip_bits_to_dec_str(const unsigned char *bits, unsigned int nbits,
else if (!comp && B_IS1(bits[mbits-idx-1])) ++val;
else if ( comp && B_IS0(bits[mbits-idx-1])) ++val;
if ((mbits-idx-1)%BBITS==0) {
/* make negative 2's complement, not 1's complement */
/* make negative 2's complement, not 1's complement */
if (comp && idx==mbits-1) ++val;
shift_in(valv,vlen,val);
val=0;
@ -202,7 +202,7 @@ unsigned vpip_bits_to_dec_str(const unsigned char *bits, unsigned int nbits,
void vpip_dec_str_to_bits(unsigned char*bits, unsigned nbits,
const char*buf, bool signed_flag)
{
/* The str string is the decimal value with the least
/* The str string is the decimal value with the least
significant digit first. This loop creates that string by
reversing the order of the buf string. For example, if the
input is "1234", str gets "4321". */