Add compiler support for `celldefine, vpiCellInstance

This patch adds support to the compiler and stub backend for
`celldefine. This matches the compiler portion of the full
support that was added to 0.10.devel. This does not change
vvp or the vvp interface since changing the interface is not
allowed in a stable branch.
This commit is contained in:
Cary R 2009-05-22 11:43:23 -07:00 committed by Stephen Williams
parent 9f07e3c16e
commit 96908e2fc5
20 changed files with 99 additions and 53 deletions

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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com) * Copyright (c) 1998-2009 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -29,6 +29,7 @@ Module::Module(perm_string n)
: PScope(n) : PScope(n)
{ {
library_flag = false; library_flag = false;
is_cell = false;
default_nettype = NetNet::NONE; default_nettype = NetNet::NONE;
} }

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@ -74,6 +74,8 @@ class Module : public PScope, public LineInfo {
other effect. */ other effect. */
bool library_flag; bool library_flag;
bool is_cell;
NetNet::Type default_nettype; NetNet::Type default_nettype;
/* specparams are simpler then other params, in that they have /* specparams are simpler then other params, in that they have

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@ -1081,6 +1081,7 @@ void NetScope::dump(ostream&o) const
print_type(o); print_type(o);
if (is_auto()) o << " (automatic)"; if (is_auto()) o << " (automatic)";
if (is_cell()) o << " (cell)";
o << endl; o << endl;
for (unsigned idx = 0 ; idx < attr_cnt() ; idx += 1) for (unsigned idx = 0 ; idx < attr_cnt() ; idx += 1)

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@ -479,6 +479,8 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
elaborate_scope_events_(des, scope, events); elaborate_scope_events_(des, scope, events);
scope->is_cell(is_cell);
return des->errors == 0; return des->errors == 0;
} }

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@ -161,6 +161,7 @@ ivl_scope_event
ivl_scope_events ivl_scope_events
ivl_scope_file ivl_scope_file
ivl_scope_is_auto ivl_scope_is_auto
ivl_scope_is_cell
ivl_scope_lineno ivl_scope_lineno
ivl_scope_logs ivl_scope_logs
ivl_scope_log ivl_scope_log

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@ -1537,6 +1537,9 @@ extern unsigned ivl_parameter_lineno(ivl_parameter_t net);
* ivl_scope_is_auto * ivl_scope_is_auto
* Is the task or function declared to be automatic? * Is the task or function declared to be automatic?
* *
* ivl_scope_is_cell
* Is the module defined to be a cell?
*
* ivl_scope_var * ivl_scope_var
* ivl_scope_vars * ivl_scope_vars
* REMOVED * REMOVED
@ -1614,6 +1617,7 @@ extern unsigned ivl_scope_events(ivl_scope_t net);
extern ivl_event_t ivl_scope_event(ivl_scope_t net, unsigned idx); extern ivl_event_t ivl_scope_event(ivl_scope_t net, unsigned idx);
extern const char* ivl_scope_file(ivl_scope_t net); extern const char* ivl_scope_file(ivl_scope_t net);
extern unsigned ivl_scope_is_auto(ivl_scope_t net); extern unsigned ivl_scope_is_auto(ivl_scope_t net);
extern unsigned ivl_scope_is_cell(ivl_scope_t net);
extern unsigned ivl_scope_lineno(ivl_scope_t net); extern unsigned ivl_scope_lineno(ivl_scope_t net);
extern unsigned ivl_scope_logs(ivl_scope_t net); extern unsigned ivl_scope_logs(ivl_scope_t net);
extern ivl_net_logic_t ivl_scope_log(ivl_scope_t net, unsigned idx); extern ivl_net_logic_t ivl_scope_log(ivl_scope_t net, unsigned idx);

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@ -214,26 +214,34 @@ int main(int argc, char*argv[])
FILE*precomp_out = NULL; FILE*precomp_out = NULL;
/* Define preprocessor keywords that I plan to just pass. */ /* Define preprocessor keywords that I plan to just pass. */
/* From 1364-2005 Chapter 19. */
define_macro("begin_keywords", "`begin_keywords", 1, 0);
define_macro("celldefine", "`celldefine", 1, 0); define_macro("celldefine", "`celldefine", 1, 0);
define_macro("default_decay_time", "`default_decay_time", 1, 0);
define_macro("default_nettype", "`default_nettype", 1, 0); define_macro("default_nettype", "`default_nettype", 1, 0);
define_macro("default_trireg_strength", "`default_trireg_strength", 1, 0); define_macro("end_keywords", "`end_keywords", 1, 0);
define_macro("delay_mode_distributed", "`delay_mode_distributed", 1, 0);
define_macro("delay_mode_unit", "`delay_mode_unit", 1, 0);
define_macro("delay_mode_path", "`delay_mode_path", 1, 0);
define_macro("delay_mode_zero", "`delay_mode_zero", 1, 0);
define_macro("disable_portfaults", "`disable_portfaults", 1, 0);
define_macro("enable_portfaults", "`enable_portfaults", 1, 0);
define_macro("endcelldefine", "`endcelldefine", 1, 0); define_macro("endcelldefine", "`endcelldefine", 1, 0);
define_macro("endprotect", "`endprotect", 1, 0);
define_macro("line", "`line", 1, 0); define_macro("line", "`line", 1, 0);
define_macro("nosuppress_faults", "`nosuppress_faults", 1, 0);
define_macro("nounconnected_drive", "`nounconnected_drive", 1, 0); define_macro("nounconnected_drive", "`nounconnected_drive", 1, 0);
define_macro("protect", "`protect", 1, 0); define_macro("pragma", "`pragma", 1, 0);
define_macro("resetall", "`resetall", 1, 0); define_macro("resetall", "`resetall", 1, 0);
define_macro("suppress_faults", "`suppress_faults", 1, 0);
define_macro("timescale", "`timescale", 1, 0); define_macro("timescale", "`timescale", 1, 0);
define_macro("unconnected_drive", "`unconnected_drive", 1, 0); define_macro("unconnected_drive", "`unconnected_drive", 1, 0);
/* From 1364-2005 Annex D. */
define_macro("default_decay_time", "`default_decay_time", 1, 0);
define_macro("default_trireg_strength", "`default_trireg_strength", 1, 0);
define_macro("delay_mode_distributed", "`delay_mode_distributed", 1, 0);
define_macro("delay_mode_path", "`delay_mode_path", 1, 0);
define_macro("delay_mode_unit", "`delay_mode_unit", 1, 0);
define_macro("delay_mode_zero", "`delay_mode_zero", 1, 0);
/* From other places. */
define_macro("disable_portfaults", "`disable_portfaults", 1, 0);
define_macro("enable_portfaults", "`enable_portfaults", 1, 0);
define_macro("endprotect", "`endprotect", 1, 0);
define_macro("nosuppress_faults", "`nosuppress_faults", 1, 0);
define_macro("protect", "`protect", 1, 0);
define_macro("suppress_faults", "`suppress_faults", 1, 0);
define_macro("uselib", "`uselib", 1, 0); define_macro("uselib", "`uselib", 1, 0);
include_cnt = 2; include_cnt = 2;

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@ -88,6 +88,7 @@ static list<int> keyword_mask_stack;
static int comment_enter; static int comment_enter;
static bool in_module = false; static bool in_module = false;
bool in_celldefine = false;
%} %}
%x CCOMMENT %x CCOMMENT
@ -362,28 +363,33 @@ S [afpnumkKMGT]
yylloc.first_line += 1; yylloc.first_line += 1;
BEGIN(0); } BEGIN(0); }
^{W}?`celldefine{W}?.* { in_celldefine = true; }
^{W}?`endcelldefine{W}?.* { in_celldefine = false; }
/* These are directives that I do not yet support. I think that IVL /* These are directives that I do not yet support. I think that IVL
should handle these, not an external preprocessor. */ should handle these, not an external preprocessor. */
/* From 1364-2005 Chapter 19. */
^{W}?`line{W}?.* { }
^{W}?`nounconnected_drive{W}?.* { }
^{W}?`pragme{W}?.* { }
^{W}?`resetall{W}?.* { }
^{W}?`unconnected_drive{W}?.* { }
^{W}?`celldefine{W}?.* { } /* From 1364-2005 Annex D. */
^{W}?`default_decay_time{W}?.* { } ^{W}?`default_decay_time{W}?.* { }
^{W}?`default_trireg_strength{W}?.* { } ^{W}?`default_trireg_strength{W}?.* { }
^{W}?`delay_mode_distributed{W}?.* { } ^{W}?`delay_mode_distributed{W}?.* { }
^{W}?`delay_mode_unit{W}?.* { }
^{W}?`delay_mode_path{W}?.* { } ^{W}?`delay_mode_path{W}?.* { }
^{W}?`delay_mode_unit{W}?.* { }
^{W}?`delay_mode_zero{W}?.* { } ^{W}?`delay_mode_zero{W}?.* { }
/* From other places. */
^{W}?`disable_portfaults{W}?.* { } ^{W}?`disable_portfaults{W}?.* { }
^{W}?`enable_portfaults{W}?.* { } ^{W}?`enable_portfaults{W}?.* { }
^{W}?`endcelldefine{W}?.* { }
`endprotect { } `endprotect { }
^{W}?`line{W}?.* { }
^{W}?`nosuppress_faults{W}?.* { } ^{W}?`nosuppress_faults{W}?.* { }
^{W}?`nounconnected_drive{W}?.* { }
`protect { } `protect { }
^{W}?`resetall{W}?.* { }
^{W}?`suppress_faults{W}?.* { } ^{W}?`suppress_faults{W}?.* { }
^{W}?`unconnected_drive{W}?.* { }
^{W}?`uselib{W}?.* { } ^{W}?`uselib{W}?.* { }
^{W}?`begin_keywords{W}? { BEGIN(PPBEGIN_KEYWORDS); } ^{W}?`begin_keywords{W}? { BEGIN(PPBEGIN_KEYWORDS); }

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@ -41,6 +41,7 @@ NetScope::NetScope(NetScope*up, const hname_t&n, NetScope::TYPE t)
events_ = 0; events_ = 0;
lcounter_ = 0; lcounter_ = 0;
is_auto_ = false; is_auto_ = false;
is_cell_ = false;
if (up) { if (up) {
default_nettype_ = up->default_nettype(); default_nettype_ = up->default_nettype();

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@ -761,6 +761,10 @@ class NetScope : public Attrib {
void is_auto(bool is_auto__) { is_auto_ = is_auto__; }; void is_auto(bool is_auto__) { is_auto_ = is_auto__; };
bool is_auto() const { return is_auto_; }; bool is_auto() const { return is_auto_; };
/* Is the module a cell (is in a `celldefine) */
void is_cell(bool is_cell__) { is_cell_ = is_cell__; };
bool is_cell() const { return is_cell_; };
const NetTaskDef* task_def() const; const NetTaskDef* task_def() const;
const NetFuncDef* func_def() const; const NetFuncDef* func_def() const;
@ -908,7 +912,7 @@ class NetScope : public Attrib {
NetScope*sub_; NetScope*sub_;
unsigned lcounter_; unsigned lcounter_;
bool is_auto_; bool is_auto_, is_cell_;
}; };
/* /*

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@ -1923,7 +1923,7 @@ module : attribute_list_opt module_start IDENTIFIER
{ pform_module_set_ports($6); } { pform_module_set_ports($6); }
module_item_list_opt module_item_list_opt
K_endmodule K_endmodule
{ pform_endmodule($3); { pform_endmodule($3, in_celldefine);
delete[]$3; delete[]$3;
} }

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@ -1,7 +1,7 @@
#ifndef __parse_misc_H #ifndef __parse_misc_H
#define __parse_misc_H #define __parse_misc_H
/* /*
* Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com) * Copyright (c) 1998-2009 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -65,4 +65,6 @@ extern ostream& operator << (ostream&, const YYLTYPE&loc);
extern unsigned error_count, warn_count; extern unsigned error_count, warn_count;
extern unsigned long based_size; extern unsigned long based_size;
extern bool in_celldefine;
#endif #endif

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@ -449,11 +449,12 @@ void pform_module_set_ports(vector<Module::port_t*>*ports)
} }
} }
void pform_endmodule(const char*name) void pform_endmodule(const char*name, bool in_celldefine)
{ {
assert(pform_cur_module); assert(pform_cur_module);
perm_string mod_name = pform_cur_module->mod_name(); perm_string mod_name = pform_cur_module->mod_name();
assert(strcmp(name, mod_name) == 0); assert(strcmp(name, mod_name) == 0);
pform_cur_module->is_cell = in_celldefine;
map<perm_string,Module*>::const_iterator test = map<perm_string,Module*>::const_iterator test =
pform_modules.find(mod_name); pform_modules.find(mod_name);

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@ -159,7 +159,7 @@ extern void pform_module_define_port(const struct vlltype&li,
extern Module::port_t* pform_module_port_reference(perm_string name, extern Module::port_t* pform_module_port_reference(perm_string name,
const char*file, const char*file,
unsigned lineno); unsigned lineno);
extern void pform_endmodule(const char*); extern void pform_endmodule(const char*, bool in_celldefine);
extern void pform_make_udp(perm_string name, list<perm_string>*parms, extern void pform_make_udp(perm_string name, list<perm_string>*parms,
svector<PWire*>*decl, list<string>*table, svector<PWire*>*decl, list<string>*table,

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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com) * Copyright (c) 1998-2009 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -1147,7 +1147,9 @@ void Module::dump(ostream&out) const
out << " *) "; out << " *) ";
} }
out << "module " << mod_name() << ";" << endl; out << "module " << mod_name() << ";";
if (is_cell) out << " // Is in `celldefine.";
out << endl;
for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) { for (unsigned idx = 0 ; idx < ports.size() ; idx += 1) {
port_t*cur = ports[idx]; port_t*cur = ports[idx];

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@ -1655,6 +1655,12 @@ extern "C" unsigned ivl_scope_is_auto(ivl_scope_t net)
return net->is_auto; return net->is_auto;
} }
extern "C" unsigned ivl_scope_is_cell(ivl_scope_t net)
{
assert(net);
return net->is_cell;
}
extern "C" unsigned ivl_scope_lineno(ivl_scope_t net) extern "C" unsigned ivl_scope_lineno(ivl_scope_t net)
{ {
assert(net); assert(net);

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@ -2389,6 +2389,7 @@ void dll_target::scope(const NetScope*net)
scop->nattr = net->attr_cnt(); scop->nattr = net->attr_cnt();
scop->attr = fill_in_attributes(net); scop->attr = fill_in_attributes(net);
scop->is_auto = net->is_auto(); scop->is_auto = net->is_auto();
scop->is_cell = net->is_cell();
switch (net->type()) { switch (net->type()) {
case NetScope::MODULE: case NetScope::MODULE:

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@ -606,6 +606,8 @@ struct ivl_scope_s {
ivl_statement_t def; ivl_statement_t def;
unsigned is_auto; unsigned is_auto;
unsigned is_cell;
unsigned ports; unsigned ports;
ivl_signal_t*port; ivl_signal_t*port;

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@ -1533,7 +1533,8 @@ static int show_scope(ivl_scope_t net, void*x)
is_auto = ivl_scope_is_auto(net) ? "automatic " : ""; is_auto = ivl_scope_is_auto(net) ? "automatic " : "";
switch (ivl_scope_type(net)) { switch (ivl_scope_type(net)) {
case IVL_SCT_MODULE: case IVL_SCT_MODULE:
fprintf(out, " module %s", ivl_scope_tname(net)); fprintf(out, " module %s%s", ivl_scope_tname(net),
ivl_scope_is_cell(net) ? " (cell)" : "");
break; break;
case IVL_SCT_FUNCTION: case IVL_SCT_FUNCTION:
fprintf(out, " function %s%s", is_auto, ivl_scope_tname(net)); fprintf(out, " function %s%s", is_auto, ivl_scope_tname(net));

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@ -304,33 +304,34 @@ typedef struct t_vpi_delay {
#define vpiCallback 1000 #define vpiCallback 1000
/* PROPERTIES */ /* PROPERTIES */
#define vpiUndefined (-1) #define vpiUndefined (-1)
#define vpiType 1 #define vpiType 1
#define vpiName 2 #define vpiName 2
#define vpiFullName 3 #define vpiFullName 3
#define vpiSize 4 #define vpiSize 4
#define vpiFile 5 #define vpiFile 5
#define vpiLineNo 6 #define vpiLineNo 6
#define vpiTopModule 7 #define vpiTopModule 7
#define vpiDefName 9 #define vpiCellInstance 8
#define vpiDefName 9
#define vpiTimeUnit 11 #define vpiTimeUnit 11
#define vpiTimePrecision 12 #define vpiTimePrecision 12
#define vpiDefFile 15 #define vpiDefFile 15
#define vpiDefLineNo 16 #define vpiDefLineNo 16
#define vpiNetType 22 #define vpiNetType 22
# define vpiWire 1 # define vpiWire 1
#define vpiArray 28 #define vpiArray 28
#define vpiEdge 36 #define vpiEdge 36
# define vpiNoEdge 0x00 /* No edge */ # define vpiNoEdge 0x00 /* No edge */
# define vpiEdge01 0x01 /* 0 --> 1 */ # define vpiEdge01 0x01 /* 0 --> 1 */
# define vpiEdge10 0x02 /* 1 --> 0 */ # define vpiEdge10 0x02 /* 1 --> 0 */
# define vpiEdge0x 0x04 /* 0 --> x */ # define vpiEdge0x 0x04 /* 0 --> x */
# define vpiEdgex1 0x08 /* x --> 1 */ # define vpiEdgex1 0x08 /* x --> 1 */
# define vpiEdge1x 0x10 /* 1 --> x */ # define vpiEdge1x 0x10 /* 1 --> x */
# define vpiEdgex0 0x20 /* x --> 0 */ # define vpiEdgex0 0x20 /* x --> 0 */
# define vpiPosedge (vpiEdgex1|vpiEdge01|vpiEdge0x) # define vpiPosedge (vpiEdgex1|vpiEdge01|vpiEdge0x)
# define vpiNegedge (vpiEdgex0|vpiEdge10|vpiEdge1x) # define vpiNegedge (vpiEdgex0|vpiEdge10|vpiEdge1x)
# define vpiAnyEdge (vpiPosedge|vpiNegedge) # define vpiAnyEdge (vpiPosedge|vpiNegedge)
#define vpiConstType 40 #define vpiConstType 40
# define vpiDecConst 1 # define vpiDecConst 1
# define vpiRealConst 2 # define vpiRealConst 2