luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix signed/unsigned compare warning 

Fix a signed/unsigned comparison warning on RHEL 5.
This commit is contained in:
Cary R 2012-02-22 15:08:24 -08:00
parent 51ef541969
commit 952b84fba3
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
elab_lval.cc
View File

@ -480,7 +480,7 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
// Special case: The range winds up selecting the entire // Special case: The range winds up selecting the entire
// vector. Treat this as no part select at all. // vector. Treat this as no part select at all.
if (loff == 0 && moff == (reg->vector_width()-1)) { if (loff == 0 && moff == (long)(reg->vector_width()-1)) {
return true; return true;
} }
@ -489,7 +489,7 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
converted to normalized form so is relative the converted to normalized form so is relative the
variable pins. */ variable pins. */
if (loff < 0 || moff >= (signed)reg->vector_width()) { if (loff < 0 || moff >= (long)reg->vector_width()) {
cerr << get_fileline() << ": warning: Part select " cerr << get_fileline() << ": warning: Part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]" << reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl; << " is out of range." << endl;