Add regression tests for continue/break in constant functions

Check that continue and break are supported in constant functions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/constfunc16.v

@@ -0,0 +1,39 @@
+// Check that break and continue are supported in constant functions in for
+// loops
+
+module test;
+
+  function automatic integer f1(integer x);
+    integer j = 0;
+    for (integer i = 0; i < 10; i++) begin
+      if (i >= x) begin
+        break;
+      end
+      j++;
+    end
+    return j;
+  endfunction
+
+  function automatic integer f2(integer x);
+    integer j = 0;
+    for (integer i = 0; i < x; i++) begin
+      if (i % 2 == 0) begin
+        continue;
+      end
+      j++;
+    end
+    return j;
+  endfunction
+
+  reg [f1(3):0] x;
+  reg [f2(6):0] y;
+
+  initial begin
+    if ($bits(x) === 4 && $bits(y) === 4) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule

ivtest/ivltests/constfunc17.v

@@ -0,0 +1,43 @@
+// Check that break and continue are supported in constant functions in while
+// loops
+
+module test;
+
+  function automatic integer f1(integer x);
+    integer j = 0;
+    integer i = 0;
+    while (i < 10) begin
+      if (i >= x) begin
+        break;
+      end
+      j++;
+      i++;
+    end
+    return j;
+  endfunction
+
+  function automatic integer f2(integer x);
+    integer j = 0;
+    integer i = 0;
+    while (i < x) begin
+      i++;
+      if (i % 2 == 0) begin
+        continue;
+      end
+      j++;
+    end
+    return j;
+  endfunction
+
+  reg [f1(3):0] x;
+  reg [f2(6):0] y;
+
+  initial begin
+    if ($bits(x) === 4 && $bits(y) === 4) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule

ivtest/ivltests/constfunc18.v

@@ -0,0 +1,41 @@
+// Check that break and continue are supported in constant functions in repeat
+// loops
+
+module test;
+
+  function automatic integer f1(integer x);
+    integer j = 0;
+    repeat(10) begin
+      if (j >= x) begin
+        break;
+      end
+      j++;
+    end
+    return j;
+  endfunction
+
+  function automatic integer f2(integer x);
+    integer j = 0;
+    integer i = 0;
+    repeat(x) begin
+      i++;
+      if (i % 2 == 0) begin
+        continue;
+      end
+      j++;
+    end
+    return j;
+  endfunction
+
+  reg [f1(3):0] x;
+  reg [f2(6):0] y;
+
+  initial begin
+    if ($bits(x) === 4 && $bits(y) === 4) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule

ivtest/ivltests/constfunc19.v

@@ -0,0 +1,43 @@
+// Check that break and continue are supported in constant functions in do-while
+// loops
+
+module test;
+
+  function automatic integer f1(integer x);
+    integer j = 0;
+    integer i = 0;
+    do begin
+      if (i >= x) begin
+        break;
+      end
+      j++;
+      i++;
+    end while (i < 10);
+    return j;
+  endfunction
+
+  function automatic integer f2(integer x);
+    integer j = 0;
+    integer i = 0;
+    do begin
+      i++;
+      if (i % 2 == 0) begin
+        continue;
+      end
+      j++;
+    end while (i < x);
+    return j;
+  endfunction
+
+  reg [f1(3):0] x;
+  reg [f2(6):0] y;
+
+  initial begin
+    if ($bits(x) === 4 && $bits(y) === 4) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule

ivtest/ivltests/constfunc20.v

@@ -0,0 +1,32 @@
+// Check that break and continue are supported in constant functions in forever
+// loops
+
+module test;
+
+  function automatic integer f(integer x);
+    integer j = 0;
+    integer i = 0;
+    forever begin
+      i++;
+      if (i == x) begin
+        break;
+      end
+      if (i % 2 == 0) begin
+        continue;
+      end
+      j++;
+    end
+    return j;
+  endfunction
+
+  reg [f(10):0] x;
+
+  initial begin
+    if ($bits(x) === 6) begin
+      $display("PASSED");
+    end else begin
+      $display("FAILED");
+    end
+  end
+
+endmodule

ivtest/regress-vvp.list

@@ -10,6 +10,11 @@ case2				vvp_tests/case2.json
 case2-S				vvp_tests/case2-S.json
 case3				vvp_tests/case3.json
 casex_synth			vvp_tests/casex_synth.json
+constfunc16			vvp_tests/constfunc16.json
+constfunc17			vvp_tests/constfunc17.json
+constfunc18			vvp_tests/constfunc18.json
+constfunc19			vvp_tests/constfunc19.json
+constfunc20			vvp_tests/constfunc20.json
 dffsynth			vvp_tests/dffsynth.json
 dffsynth-S			vvp_tests/dffsynth-S.json
 dffsynth2			vvp_tests/dffsynth2.json

ivtest/vvp_tests/constfunc16.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "constfunc16.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/constfunc17.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "constfunc17.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/constfunc18.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "constfunc18.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/constfunc19.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "constfunc19.v",
+    "iverilog-args" : [ "-g2009" ]
+}

ivtest/vvp_tests/constfunc20.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "constfunc20.v",
+    "iverilog-args" : [ "-g2009" ]
+}