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Careful with wires connected to multiple ports.
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@@ -17,24 +17,37 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: Module.cc,v 1.8 1999/12/11 05:45:41 steve Exp $"
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#ident "$Id: Module.cc,v 1.9 2000/01/09 20:37:57 steve Exp $"
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#endif
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# include "Module.h"
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# include "PGate.h"
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# include "PWire.h"
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# include <assert.h>
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Module::Module(const string&name, const svector<Module::port_t*>*pp)
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: name_(name)
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{
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if (pp) {
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// Save the list of ports, then scan the list to make
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// the implicit wires. Add those wires to the wire map.
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ports_ = *pp;
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for (unsigned idx = 0 ; idx < ports_.count() ; idx += 1) {
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port_t*cur = ports_[idx];
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if (cur == 0)
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continue;
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for (unsigned jdx = 0 ; jdx < cur->wires.count() ; jdx += 1)
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add_wire(cur->wires[jdx]);
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// The port can actually be a list of wires, to
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// remember to scan the set. Also note the case
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// where a wire may be connected to multiple
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// ports, and reuse the link if that happens.
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for (unsigned jdx = 0; jdx < cur->wires.count(); jdx += 1) {
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PWire*tmp = add_wire(cur->wires[jdx]);
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if (tmp != cur->wires[jdx]) {
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delete cur->wires[jdx];
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cur->wires[jdx] = tmp;
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}
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}
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}
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}
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}
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@@ -54,9 +67,14 @@ void Module::add_function(const string &name, PFunction *func)
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funcs_[name] = func;
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}
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void Module::add_wire(PWire*wire)
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PWire* Module::add_wire(PWire*wire)
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{
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wires_.push_back(wire);
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PWire*&ep = wires_[wire->name()];
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if (ep) return ep;
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assert(ep == 0);
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ep = wire;
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return wire;
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}
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void Module::add_behavior(PProcess*b)
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@@ -86,17 +104,13 @@ unsigned Module::find_port(const string&name) const
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}
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PWire* Module::get_wire(const string&name)
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PWire* Module::get_wire(const string&name) const
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{
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for (list<PWire*>::iterator cur = wires_.begin()
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; cur != wires_.end()
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; cur ++ ) {
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if ((*cur)->name() == name)
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return *cur;
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}
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return 0;
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map<string,PWire*>::const_iterator obj = wires_.find(name);
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if (obj == wires_.end())
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return 0;
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else
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return (*obj).second;
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}
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PGate* Module::get_gate(const string&name)
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@@ -115,6 +129,9 @@ PGate* Module::get_gate(const string&name)
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/*
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* $Log: Module.cc,v $
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* Revision 1.9 2000/01/09 20:37:57 steve
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* Careful with wires connected to multiple ports.
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*
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* Revision 1.8 1999/12/11 05:45:41 steve
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* Fix support for attaching attributes to primitive gates.
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*
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