Handle arrays of vectors in VHDL types.
This incidentally adds binding of generic to generic instantation.
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@ -141,6 +141,9 @@ int ExpName::elaborate_rval(Entity*ent, Architecture*arc, const InterfacePort*lv
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} else if (arc->find_signal(name_)) {
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/* OK */
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} else if (ent->find_generic(name_)) {
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/* OK */
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} else {
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cerr << get_fileline() << ": error: No port or signal " << name_
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<< " to be used as r-value." << endl;
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@ -36,6 +36,18 @@ int VType::decl_t::emit(ostream&out, perm_string name) const
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int VTypeArray::emit_def(ostream&out, perm_string name) const
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{
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int errors = 0;
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if (const VTypeArray*sub = dynamic_cast<const VTypeArray*> (etype_)) {
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sub->emit_def(out, name);
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assert(dimensions() == 1);
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out << "[";
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errors += dimension(0).msb()->emit(out, 0, 0);
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out << ":";
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errors += dimension(0).lsb()->emit(out, 0, 0);
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out << "] ";
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return errors;
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}
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const VTypePrimitive*base = dynamic_cast<const VTypePrimitive*> (etype_);
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assert(base != 0);
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assert(dimensions() == 1);
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@ -58,8 +70,6 @@ int VTypeArray::emit_def(ostream&out, perm_string name) const
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int VTypeArray::emit_decl(ostream&out, perm_string name, bool reg_flag) const
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{
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int errors = 0;
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const VTypePrimitive*base = dynamic_cast<const VTypePrimitive*> (etype_);
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assert(base != 0);
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assert(dimensions() == 1);
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if (reg_flag)
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