Spelling fixes

All are in comments and .txt files except for one in the Architecture::Statement dump message.

ivlpp/ivlpp.txt

@@ -49,7 +49,7 @@ valid options include:
 
 	-f <path>
 	    Read ivlpp input files from a file list. There can be no
-	    more then one file list.
+	    more than one file list.
 
 	-I <dir>
 	    Add a directory to the include path. Normally, only "." is

netlist.h

@@ -1669,7 +1669,7 @@ class NetExpr  : public LineInfo {
 	//  rise/fall/decay: Attach these delays to the driver for the
 	//                   expression output.
 	//
-	//  drive0/drive1: Attach these strengths tp the driver for
+	//  drive0/drive1: Attach these strengths to the driver for
 	//                 the expression output.
       virtual NetNet*synthesize(Design*des, NetScope*scope, NetExpr*root);
 

pform.cc

@@ -116,7 +116,7 @@ void parm_to_defparam_list(const string&param)
     if (*value == '"') {    // string type
         char *buf = strdup (value);
         char *buf_ptr = buf+1;
-        // Parse untill another '"' or '\0'
+        // Parse until another '"' or '\0'
         while (*buf_ptr != '"' && *buf_ptr != '\0') {
             buf_ptr++;
             // Check for escape, especially '\"', which does not mean the

tgt-vhdl/stmt.cc

@@ -116,7 +116,7 @@ static int draw_stask_display(vhdl_procedural *proc,
 
                switch (*p) {
                case 'm':
-                  // TOOD: we can get the module name via attributes
+                  // TODO: we can get the module name via attributes
                   cerr << "Warning: no VHDL translation for %m format code"
                        << endl;
                   break;
@@ -1603,7 +1603,7 @@ int draw_utask(vhdl_procedural *proc, stmt_container *container,
 
    // TODO: adding some comments to the output would be helpful
 
-   // TOOD: this completely ignores parameters!
+   // TODO: this completely ignores parameters!
    draw_stmt(proc, container, ivl_scope_def(tscope), false);
 
    return 0;

vhdlpp/debug.cc

@@ -116,7 +116,7 @@ void Architecture::dump(ostream&out, perm_string of_entity) const
 
 void Architecture::Statement::dump(ostream&out) const
 {
-      out << "   Architecutre::Statement at file=" << get_fileline() << endl;
+      out << "   Architecture::Statement at file=" << get_fileline() << endl;
 }
 
 void Signal::dump(ostream&out) const

vhdlpp/expression.h

@@ -37,9 +37,9 @@ class Expression : public LineInfo {
       Expression();
       virtual ~Expression() =0;
 
-	// The emit virtual method is called bu architecture emit to
+	// The emit virtual method is called by architecture emit to
 	// output the generated code for the expression. The derived
-	// class fills in the details of what exactly happend.
+	// class fills in the details of what exactly happened.
       virtual int emit(ostream&out, Entity*ent, Architecture*arc) =0;
 
 	// The evaluate virtual method tries to evaluate expressions
@@ -49,9 +49,9 @@ class Expression : public LineInfo {
       virtual bool evaluate(int64_t&val) const;
 
 	// This method returns true if the drawn Verilog for this
-	// expression is a primary. A containing expressin can use
+	// expression is a primary. A containing expression can use
 	// this method to know if it needs to wrap parentheses. This
-	// is somewhile optional, so it is better to return false if
+	// is somewhat optional, so it is better to return false if
 	// not certain. The default implementation does return false.
       virtual bool is_primary(void) const;
 

vhdlpp/parse_api.h

@@ -54,7 +54,7 @@ extern int yylex(void);
 extern int yyparse(void);
 
 /*
- * Use this functio during parse to generate error messages. The "loc"
+ * Use this function during parse to generate error messages. The "loc"
  * is the location of the token that triggered the error, and the fmt
  * is printf-style format.
  */

vvp/README.txt

@@ -282,7 +282,7 @@ general syntax of a variable is:
 	<label> .var/s "name", <msb> <lsb>; Signed logic variable
 	<label> .var/2u "name", <msb> <lsb>; Unsigned bool/bit variable
 	<label> .var/2s "name", <msb> <lsb>; Signed bool/bit variable
-	<label> .var/real "name", <msb>, <lsb>; real varibale
+	<label> .var/real "name", <msb>, <lsb>; real variable
 	<label> .var/i "name", <msb>, <lsb>; vpiIntegerVar variable
 
 The "name" is the declared base name of the original variable, for the
@@ -757,7 +757,7 @@ code is undefined.
 * Thread Context
 
 The context of a thread is all the local data that only that thread
-can address. The local data is broken into two addresses spaces: bit
+can address. The local data is broken into two address spaces: bit
 memory and word memory.
 
 The bit memory is a region of 4-value bits (0,1,x,z) that can be
@@ -1109,8 +1109,8 @@ associated with that variable or event.
 
 Each VVP thread keeps track of its current write context and current
 read context. For threads executing in a static scope, these are both
-initialised to null values. For threads executing in an automatically
+initialized to null values. For threads executing in an automatically
-allocated scope, these are both initialised to refer to the context
+allocated scope, these are both initialized to refer to the context
 allocated to that scope.
 
 Before starting the copying of the input parameters of an automatic

vvp/vvp_net.cc

@@ -40,7 +40,7 @@
 permaheap vvp_net_fun_t::heap_;
 permaheap vvp_net_fil_t::heap_;
 
-// Allocate around 1Megbytes/chunk.
+// Allocate around 1Megabyte/chunk.
 static const size_t VVP_NET_CHUNK = 1024*1024/sizeof(vvp_net_t);
 static vvp_net_t*vvp_net_alloc_table = NULL;
 #ifdef CHECK_WITH_VALGRIND