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Make sure signal names conform to VHDL rules

This commit is contained in:
Nick Gasson 2008-06-16 17:37:17 +01:00
parent ce72eb4eb4
commit 83a7796b74
1 changed files with 13 additions and 8 deletions
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17
tgt-vhdl/scope.cc
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@ -140,19 +140,24 @@ static void declare_signals(vhdl_arch *arch, ivl_scope_t scope)
remember_signal(sig, arch->get_parent()); remember_signal(sig, arch->get_parent());
const char *name = ivl_signal_basename(sig); // Make sure the signal name conforms to VHDL naming rules
std::string name(ivl_signal_basename(sig));
if (name[0] == '_')
name.insert(0, "VL");
rename_signal(sig, name.c_str());
ivl_signal_port_t mode = ivl_signal_port(sig); ivl_signal_port_t mode = ivl_signal_port(sig);
switch (mode) { switch (mode) {
case IVL_SIP_NONE: case IVL_SIP_NONE:
arch->add_decl(new vhdl_signal_decl(name, sig_type)); arch->add_decl(new vhdl_signal_decl(name.c_str(), sig_type));
break; break;
case IVL_SIP_INPUT: case IVL_SIP_INPUT:
arch->get_parent()->add_port arch->get_parent()->add_port
(new vhdl_port_decl(name, sig_type, VHDL_PORT_IN)); (new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_IN));
break; break;
case IVL_SIP_OUTPUT: case IVL_SIP_OUTPUT:
arch->get_parent()->add_port arch->get_parent()->add_port
(new vhdl_port_decl(name, sig_type, VHDL_PORT_OUT)); (new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT));
if (ivl_signal_type(sig) == IVL_SIT_REG) { if (ivl_signal_type(sig) == IVL_SIT_REG) {
// A registered output // A registered output
@ -171,13 +176,13 @@ static void declare_signals(vhdl_arch *arch, ivl_scope_t scope)
// connect the register to the output // connect the register to the output
arch->add_stmt arch->add_stmt
(new vhdl_cassign_stmt (new vhdl_cassign_stmt
(new vhdl_var_ref(name, NULL), (new vhdl_var_ref(name.c_str(), NULL),
new vhdl_var_ref(newname.c_str(), NULL))); new vhdl_var_ref(newname.c_str(), NULL)));
} }
break; break;
case IVL_SIP_INOUT: case IVL_SIP_INOUT:
arch->get_parent()->add_port arch->get_parent()->add_port
(new vhdl_port_decl(name, sig_type, VHDL_PORT_INOUT)); (new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_INOUT));
break; break;
} }
} }