Merge branch 'x-sizer3'
This commit is contained in:
Stephen Williams
commit
830083d99b
103
parse.y
103
parse.y
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@ -607,7 +607,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%type <property_qualifier> class_item_qualifier_opt property_qualifier_opt
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%type <property_qualifier> random_qualifier
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%type <ranges> range range_opt variable_dimension
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%type <ranges> variable_dimension
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%type <ranges> dimensions_opt dimensions
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%type <nettype> net_type var_type net_type_opt
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@ -973,7 +973,7 @@ data_declaration /* IEEE1800-2005: A.2.1.3 */
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;
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data_type /* IEEE1800-2005: A.2.2.1 */
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: integer_vector_type unsigned_signed_opt range_opt
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: integer_vector_type unsigned_signed_opt dimensions_opt
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{ ivl_variable_type_t use_vtype = $1;
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bool reg_flag = false;
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if (use_vtype == IVL_VT_NO_TYPE) {
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@ -1012,7 +1012,7 @@ data_type /* IEEE1800-2005: A.2.2.1 */
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tmp->reg_flag = true;
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$$ = tmp;
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}
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| TYPE_IDENTIFIER range_opt
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| TYPE_IDENTIFIER dimensions_opt
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{ if ($2) $$ = new parray_type_t($1, $2);
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else $$ = $1;
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}
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@ -1038,13 +1038,13 @@ data_type /* IEEE1800-2005: A.2.2.1 */
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data_type_or_implicit /* IEEE1800-2005: A.2.2.1 */
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: data_type
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{ $$ = $1; }
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| signing range_opt
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| signing dimensions_opt
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{ vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, $1, $2);
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tmp->implicit_flag = true;
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FILE_NAME(tmp, @1);
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$$ = tmp;
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}
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| range
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| dimensions
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{ vector_type_t*tmp = new vector_type_t(IVL_VT_LOGIC, false, $1);
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tmp->implicit_flag = true;
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FILE_NAME(tmp, @1);
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@ -1796,7 +1796,7 @@ task_declaration /* IEEE1800-2005: A.2.7 */
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tf_port_declaration /* IEEE1800-2005: A.2.7 */
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: port_direction K_reg_opt unsigned_signed_opt range_opt list_of_identifiers ';'
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: port_direction K_reg_opt unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ vector<pform_tf_port_t>*tmp = pform_make_task_ports(@1, $1,
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$2 ? IVL_VT_LOGIC :
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IVL_VT_NO_TYPE,
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@ -1844,7 +1844,7 @@ tf_port_declaration /* IEEE1800-2005: A.2.7 */
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tf_port_item /* IEEE1800-2005: A.2.7 */
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: port_direction_opt data_type_or_implicit IDENTIFIER range_opt tf_port_item_expr_opt
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: port_direction_opt data_type_or_implicit IDENTIFIER dimensions_opt tf_port_item_expr_opt
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{ vector<pform_tf_port_t>*tmp;
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NetNet::PortType use_port_type = $1==NetNet::PIMPLICIT? NetNet::PINPUT : $1;
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perm_string name = lex_strings.make($3);
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@ -2169,6 +2169,15 @@ type_declaration
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pform_set_typedef(name, tmp);
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delete[]$2;
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}
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| K_typedef data_type TYPE_IDENTIFIER ';'
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{ yyerror(@3, "error: Typedef identifier is already a type name."); }
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| K_typedef error ';'
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{ yyerror(@2, "error: Syntax error in typedef clause.");
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yyerrok;
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}
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;
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/* The structure for an enumeration data type is the keyword "enum",
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@ -2204,7 +2213,7 @@ enum_data_type
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enum_type->range.reset(make_range_from_width(integer_width));
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$$ = enum_type;
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}
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| K_enum K_logic unsigned_signed_opt range '{' enum_name_list '}'
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| K_enum K_logic unsigned_signed_opt dimensions '{' enum_name_list '}'
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{ enum_type_t*enum_type = new enum_type_t;
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FILE_NAME(enum_type, @1);
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enum_type->names .reset($6);
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@ -2213,7 +2222,7 @@ enum_data_type
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enum_type->range.reset($4);
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$$ = enum_type;
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}
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| K_enum K_reg unsigned_signed_opt range '{' enum_name_list '}'
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| K_enum K_reg unsigned_signed_opt dimensions '{' enum_name_list '}'
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{ enum_type_t*enum_type = new enum_type_t;
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FILE_NAME(enum_type, @1);
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enum_type->names .reset($6);
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@ -2222,7 +2231,7 @@ enum_data_type
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enum_type->range.reset($4);
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$$ = enum_type;
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}
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| K_enum K_bit unsigned_signed_opt range '{' enum_name_list '}'
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| K_enum K_bit unsigned_signed_opt dimensions '{' enum_name_list '}'
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{ enum_type_t*enum_type = new enum_type_t;
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FILE_NAME(enum_type, @1);
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enum_type->names .reset($6);
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@ -2425,12 +2434,12 @@ defparam_assign
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;
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defparam_assign_list
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: defparam_assign
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| range defparam_assign
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{ yyerror(@1, "error: defparam may not include a range.");
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delete $1;
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}
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| defparam_assign_list ',' defparam_assign
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: defparam_assign
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| dimensions defparam_assign
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{ yyerror(@1, "error: defparam may not include a range.");
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delete $1;
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}
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| defparam_assign_list ',' defparam_assign
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;
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delay1
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@ -3471,7 +3480,7 @@ gate_instance
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$$ = tmp;
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}
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| IDENTIFIER range '(' expression_list_with_nuls ')'
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| IDENTIFIER dimensions '(' expression_list_with_nuls ')'
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{ lgate*tmp = new lgate;
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list<pform_range_t>*rng = $2;
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tmp->name = $1;
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@ -3497,7 +3506,7 @@ gate_instance
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/* Degenerate modules can have no ports. */
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| IDENTIFIER range
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| IDENTIFIER dimensions
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{ lgate*tmp = new lgate;
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list<pform_range_t>*rng = $2;
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tmp->name = $1;
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@ -3526,7 +3535,7 @@ gate_instance
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$$ = tmp;
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}
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| IDENTIFIER range '(' port_name_list ')'
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| IDENTIFIER dimensions '(' port_name_list ')'
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{ lgate*tmp = new lgate;
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list<pform_range_t>*rng = $2;
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tmp->name = $1;
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@ -3555,7 +3564,7 @@ gate_instance
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$$ = tmp;
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}
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| IDENTIFIER range '(' error ')'
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| IDENTIFIER dimensions '(' error ')'
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{ lgate*tmp = new lgate;
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tmp->name = $1;
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tmp->parms = 0;
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@ -3773,7 +3782,7 @@ list_of_port_declarations
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;
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port_declaration
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: attribute_list_opt K_input net_type_opt data_type_or_implicit IDENTIFIER
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: attribute_list_opt K_input net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($5);
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ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
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@ -3787,6 +3796,10 @@ port_declaration
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port_declaration_context.range = 0;
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port_declaration_context.data_type = $4;
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delete[]$5;
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if ($6) {
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yyerror(@6, "sorry: Input ports with unpacked dimensions not supported.");
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delete $6;
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}
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$$ = ptmp;
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}
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| attribute_list_opt
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@ -3807,7 +3820,7 @@ port_declaration
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delete[]$4;
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$$ = ptmp;
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}
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| attribute_list_opt K_inout net_type_opt data_type_or_implicit IDENTIFIER
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| attribute_list_opt K_inout net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($5);
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ptmp = pform_module_port_reference(name, @2.text, @2.first_line);
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@ -3821,6 +3834,10 @@ port_declaration
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port_declaration_context.range = 0;
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port_declaration_context.data_type = $4;
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delete[]$5;
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if ($6) {
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yyerror(@6, "sorry: Inout ports with unpacked dimensions not supported.");
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delete $6;
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}
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$$ = ptmp;
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}
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| attribute_list_opt
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@ -3841,7 +3858,7 @@ port_declaration
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delete[]$4;
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$$ = ptmp;
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}
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| attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER
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| attribute_list_opt K_output net_type_opt data_type_or_implicit IDENTIFIER dimensions_opt
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{ Module::port_t*ptmp;
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perm_string name = lex_strings.make($5);
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NetNet::Type use_type = $3;
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@ -3875,6 +3892,10 @@ port_declaration
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port_declaration_context.range = 0;
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port_declaration_context.data_type = $4;
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delete[]$5;
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if ($6) {
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yyerror(@6, "sorry: Output ports with unpacked dimensions not supported.");
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delete $6;
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}
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$$ = ptmp;
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}
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| attribute_list_opt
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@ -4283,23 +4304,23 @@ module_item
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}
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}
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| K_trireg charge_strength_opt range_opt delay3_opt list_of_identifiers ';'
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| K_trireg charge_strength_opt dimensions_opt delay3_opt list_of_identifiers ';'
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{ yyerror(@1, "sorry: trireg nets not supported.");
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delete $3;
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delete $4;
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}
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| attribute_list_opt port_direction unsigned_signed_opt range_opt delay3_opt list_of_identifiers ';'
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| attribute_list_opt port_direction unsigned_signed_opt dimensions_opt delay3_opt list_of_identifiers ';'
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{ pform_set_port_type(@2, $6, $4, $3, $2, $1); }
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/* The next two rules handle Verilog 2001 statements of the form:
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input wire signed [h:l] <list>;
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This creates the wire and sets the port type all at once. */
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| attribute_list_opt port_direction net_type unsigned_signed_opt range_opt list_of_identifiers ';'
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| attribute_list_opt port_direction net_type unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ pform_makewire(@2, $5, $4, $6, $3, $2, IVL_VT_NO_TYPE, $1, SR_BOTH); }
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| attribute_list_opt K_output var_type unsigned_signed_opt range_opt list_of_port_identifiers ';'
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| attribute_list_opt K_output var_type unsigned_signed_opt dimensions_opt list_of_port_identifiers ';'
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{ list<pair<perm_string,PExpr*> >::const_iterator pp;
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list<perm_string>*tmp = new list<perm_string>;
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for (pp = $6->begin(); pp != $6->end(); ++ pp ) {
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@ -4324,19 +4345,19 @@ module_item
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because the port declaration implies an external driver, which
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cannot be attached to a reg. These rules catch that error early. */
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| attribute_list_opt K_input var_type unsigned_signed_opt range_opt list_of_identifiers ';'
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| attribute_list_opt K_input var_type unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ pform_makewire(@2, $5, $4, $6, $3, NetNet::PINPUT,
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IVL_VT_NO_TYPE, $1);
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yyerror(@3, "error: reg variables cannot be inputs.");
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}
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| attribute_list_opt K_inout var_type unsigned_signed_opt range_opt list_of_identifiers ';'
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| attribute_list_opt K_inout var_type unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ pform_makewire(@2, $5, $4, $6, $3, NetNet::PINOUT,
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IVL_VT_NO_TYPE, $1);
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yyerror(@3, "error: reg variables cannot be inouts.");
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}
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| attribute_list_opt port_direction unsigned_signed_opt range_opt delay3_opt error ';'
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| attribute_list_opt port_direction unsigned_signed_opt dimensions_opt delay3_opt error ';'
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{ yyerror(@2, "error: Invalid variable list in port declaration.");
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if ($1) delete $1;
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if ($4) delete $4;
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@ -4720,7 +4741,7 @@ var_type
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;
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param_type
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: bit_logic_opt unsigned_signed_opt range_opt
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: bit_logic_opt unsigned_signed_opt dimensions_opt
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{ param_active_range = $3;
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param_active_signed = $2;
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if (($1 == IVL_VT_NO_TYPE) && ($3 != 0))
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@ -5112,24 +5133,6 @@ port_reference_list
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;
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/* The range is a list of variable dimensions. */
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range
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: variable_dimension
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{ $$ = $1; }
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| range variable_dimension
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{ list<pform_range_t>*tmp = $1;
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if ($2) {
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tmp->splice(tmp->end(), *$2);
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delete $2;
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}
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$$ = tmp;
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}
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;
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range_opt
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: range
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| { $$ = 0; }
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;
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dimensions_opt
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: { $$ = 0; }
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| dimensions { $$ = $1; }
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@ -5479,7 +5482,7 @@ specparam_list
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specparam_decl
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: specparam_list
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| range
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| dimensions
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{ param_active_range = $1; }
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specparam_list
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{ param_active_range = 0; }
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