Generate VHDL entities and architectures for all module scopes

tgt-vhdl/Makefile.in

@@ -49,7 +49,7 @@ dep:
 	$(CXX) $(CPPFLAGS) $(CXXFLAGS) -MD -c $< -o $*.o
 	mv $*.d dep
 
-O = vhdl.o vhdl_element.o
+O = vhdl.o vhdl_element.o scope.o process.o
 
 ifeq (@WIN32@,yes)
   TGTLDFLAGS=-L.. -livl

tgt-vhdl/vhdl.cc

@@ -25,9 +25,13 @@
 #include <fstream>
 #include <cstdarg>
 #include <cstdio>
+#include <cassert>
+#include <cstring>
 
 static int g_errors = 0;  // Total number of errors encountered
 
+static entity_list_t g_entities;  // All entities to emit
+
 /*
  * Called when an unrecoverable problem is encountered.
  */
@@ -44,14 +48,27 @@ void error(const char *fmt, ...)
    g_errors++;
 }
 
-int dummy(ivl_process_t net, void *cd)
+/*
+ * Find an entity given a type name.
+ */
+vhdl_entity *find_entity(const char *tname)
 {
-   std::cout << "process" << std::endl;
+   entity_list_t::const_iterator it;
+   for (it = g_entities.begin(); it != g_entities.end(); ++it) {
+      if (strcmp((*it)->get_name(), tname) == 0)
+         return *it;
+   }
+   return NULL;
+}
 
-   ivl_scope_t scope = ivl_process_scope(net);
+/*
-   std::cout << ivl_scope_name(scope) << std::endl;
+ * Add an entity/architecture pair to the list of entities
-   
+ * to emit.
-   return 0;
+ */
+void remember_entity(vhdl_entity* ent)
+{
+   assert(find_entity(ent->get_name()) == NULL);
+   g_entities.push_back(ent);
 }
 
 extern "C" int target_design(ivl_design_t des)
@@ -60,25 +77,18 @@ extern "C" int target_design(ivl_design_t des)
    unsigned int nroots;
    ivl_design_roots(des, &roots, &nroots);
 
+   for (unsigned int i = 0; i < nroots; i++)
+      draw_scope(roots[i], NULL);
+
+   ivl_design_process(des, draw_process, NULL);
+
+   // Write the generated elements to the output file
    const char *ofname = ivl_design_flag(des, "-o");
    std::ofstream outfile(ofname);
 
-   for (unsigned int i = 0; i < nroots; i++) {
+   entity_list_t::const_iterator it;
-      ivl_scope_t scope = roots[i];
+   for (it = g_entities.begin(); it != g_entities.end(); ++it)
-      const char *scope_name = ivl_scope_basename(scope);
+      (*it)->emit(outfile);
-      
-      // Dummy output to test regression script
-      vhdl_entity test_ent(scope_name);
-      vhdl_arch test_arch(scope_name);
-      vhdl_process test_proc;
-      test_arch.set_comment("I am a comment");
-      test_arch.add_stmt(&test_proc);
-      test_proc.set_comment("I am a process");
-      test_ent.emit(outfile);
-      test_arch.emit(outfile);
-   }
-
-   ivl_design_process(des, dummy, 0);
    
    outfile.close();
       

tgt-vhdl/vhdl_element.cc

@@ -85,8 +85,8 @@ void vhdl_element::emit_comment(std::ofstream &of, int level) const
 
 //////// ENTITY ////////
 
-vhdl_entity::vhdl_entity(const char *name)
+vhdl_entity::vhdl_entity(const char *name, vhdl_arch *arch)
-   : name_(name)
+   : name_(name), arch_(arch)
 {
 
 }
@@ -100,6 +100,7 @@ void vhdl_entity::emit(std::ofstream &of, int level) const
    newline(of, level);
    of << "end entity; ";
    blank_line(of, level);  // Extra blank line after entities
+   arch_->emit(of, level);
 }
 
 

tgt-vhdl/vhdl_element.hh

@@ -31,6 +31,8 @@ typedef std::list<vhdl_element*> element_list_t;
 
 class vhdl_element {
 public:
+   virtual ~vhdl_element() {}
+   
    virtual void emit(std::ofstream &of, int level=0) const = 0;
 
    void set_comment(std::string comment);
@@ -40,21 +42,16 @@ private:
    std::string comment_;
 };
 
-class vhdl_entity : public vhdl_element {
-public:
-   vhdl_entity(const char *name);
-
-   void emit(std::ofstream &of, int level=0) const;
-private:
-   const char *name_;
-};
-
 class vhdl_conc_stmt : public vhdl_element {
+public:
+   virtual ~vhdl_conc_stmt() {}
 };
 
 typedef std::list<vhdl_conc_stmt*> conc_stmt_list_t;
 
 class vhdl_seq_stmt : public vhdl_element {
+public:
+   virtual ~vhdl_seq_stmt() {}
 };
 
 typedef std::list<vhdl_seq_stmt*> seq_stmt_list_t;
@@ -62,6 +59,7 @@ typedef std::list<vhdl_seq_stmt*> seq_stmt_list_t;
 class vhdl_process : public vhdl_conc_stmt {
 public:
    vhdl_process(const char *name = NULL);
+   virtual ~vhdl_process() {}
 
    void emit(std::ofstream &of, int level) const;
    void add_stmt(vhdl_seq_stmt* stmt);
@@ -73,6 +71,7 @@ private:
 class vhdl_arch : public vhdl_element {
 public:
    vhdl_arch(const char *entity, const char *name="Behavioural");
+   virtual ~vhdl_arch() {}
 
    void emit(std::ofstream &of, int level=0) const;
    void add_stmt(vhdl_conc_stmt* stmt);
@@ -81,5 +80,21 @@ private:
    const char *name_, *entity_;
 };
 
+class vhdl_entity : public vhdl_element {
+public:
+   vhdl_entity(const char *name, vhdl_arch *arch);
+   virtual ~vhdl_entity() {}
+
+   void emit(std::ofstream &of, int level=0) const;
+   vhdl_arch *get_arch() const { return arch_; }
+   const char *get_name() const { return name_; }
+private:
+   const char *name_;
+   vhdl_arch *arch_;  // Entity may only have a single architecture
+};
+
+typedef std::list<vhdl_entity*> entity_list_t;
+
+
 #endif
 

tgt-vhdl/vhdl_target.h

@@ -4,7 +4,15 @@
 #include "vhdl_config.h"
 #include "ivl_target.h"
 
+#include "vhdl_element.hh"
+
 void error(const char *fmt, ...);
 
+int draw_scope(ivl_scope_t scope, void *_parent);
+int draw_process(ivl_process_t net, void *cd);
+
+void remember_entity(vhdl_entity *ent);
+vhdl_entity *find_entity(const char *tname);
+
 #endif /* #ifndef INC_VHDL_TARGET_H */