Support timescales in design units that aren't inside a module.

SystemVerilog allows tasks, functions, and classes to be defined at the
root level or inside packages, so we can't rely on an enclosing module
being present to provide the timescale.

Module.cc

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1998-2015 Stephen Williams ([email protected])
+ * Copyright (c) 1998-2016 Stephen Williams ([email protected])
  *
  *    This source code is free software; you can redistribute it
  *    and/or modify it in source code form under the terms of the GNU
@@ -36,9 +36,6 @@ Module::Module(LexicalScope*parent, perm_string n)
       program_block = false;
       uc_drive = UCD_NONE;
       timescale_warn_done = false;
-      time_unit = 0;
-      time_precision = 0;
-      time_from_timescale = false;
 }
 
 Module::~Module()