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Add support it vvm target for level-sensitive 

triggers (i.e. the Verilog wait).
 Fix display of $time is format strings.
This commit is contained in:
steve 1998-11-10 00:48:31 +00:00
parent 8705aa94c6
commit 7859de1e4e
7 changed files with 149 additions and 60 deletions
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89
t-vvm.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: t-vvm.cc,v 1.4 1998/11/09 18:55:34 steve Exp $" #ident "$Id: t-vvm.cc,v 1.5 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include <iostream> # include <iostream>
@ -445,12 +445,12 @@ void target_vvm::start_process(ostream&os, const NetProcTop*proc)
os << " { }" << endl; os << " { }" << endl;
os << " ~thread" << process_counter << "_t() { }" << endl; os << " ~thread" << process_counter << "_t() { }" << endl;
os << endl; os << endl;
os << " void go() { (this->*step_)(); }" << endl; os << " bool go() { return (this->*step_)(); }" << endl;
os << " private:" << endl; os << " private:" << endl;
os << " void (thread" << process_counter << os << " bool (thread" << process_counter <<
"_t::*step_)();" << endl; "_t::*step_)();" << endl;
os << " void step_0_() {" << endl; os << " bool step_0_() {" << endl;
} }
/* /*
@ -566,25 +566,57 @@ void target_vvm::proc_event(ostream&os, const NetPEvent*proc)
thread_step_ += 1; thread_step_ += 1;
os << setw(indent_) << "" << "step_ = &step_" << thread_step_ << os << setw(indent_) << "" << "step_ = &step_" << thread_step_ <<
"_;" << endl; "_;" << endl;
os << setw(indent_) << "" << mangle(proc->name()) <<
".wait(vvm_pevent::"; /* POSITIVE is for the wait construct, and needs to be handled
switch (proc->edge()) { specially. The structure of the generated code is:
case NetPEvent::ANYEDGE:
os << "ANYEDGE"; if (event.get()==V1) {
break; return true;
case NetPEvent::POSEDGE: } else {
os << "POSEDGE"; event.wait(vvm_pevent::POSEDGE, this);
break; return false;
case NetPEvent::NEGEDGE: }
os << "NEGEDGE";
break; This causes the wait to not even block the thread if the
case NetPEvent::POSITIVE: event value is already positive, otherwise wait for a
os << "POSITIVE"; rising edge. All the edge triggers look like this:
break;
event.wait(vvm_pevent::POSEDGE, this);
return false;
POSEDGE is replaced with the correct type for the desired
edge. */
if (proc->edge() == NetPEvent::POSITIVE) {
os << setw(indent_) << "" << "if (" <<
mangle(proc->name()) << ".get()==V1) {" << endl;
os << setw(indent_+3) << "" << "return true;" << endl;
os << setw(indent_) << "" << "} else {" << endl;
os << setw(indent_+3) << "" << mangle(proc->name()) <<
".wait(vvm_pevent::POSEDGE, this);" << endl;
os << setw(indent_+3) << "" << "return false;" << endl;
os << setw(indent_) << "" << "}" << endl;
} else {
os << setw(indent_) << "" << mangle(proc->name()) <<
".wait(vvm_pevent::";
switch (proc->edge()) {
case NetPEvent::ANYEDGE:
os << "ANYEDGE";
break;
case NetPEvent::POSITIVE:
case NetPEvent::POSEDGE:
os << "POSEDGE";
break;
case NetPEvent::NEGEDGE:
os << "NEGEDGE";
break;
}
os << ", this);" << endl;
os << setw(indent_+3) << "" << "return false;" << endl;
} }
os << ", this);" << endl;
os << " }" << endl; os << " }" << endl;
os << " void step_" << thread_step_ << "_()" << endl; os << " bool step_" << thread_step_ << "_()" << endl;
os << " {" << endl; os << " {" << endl;
proc->emit_proc_recurse(os, this); proc->emit_proc_recurse(os, this);
@ -599,8 +631,9 @@ void target_vvm::proc_delay(ostream&os, const NetPDelay*proc)
os << " step_ = &step_" << thread_step_ << "_;" << endl; os << " step_ = &step_" << thread_step_ << "_;" << endl;
os << " sim_->thread_delay(" << proc->delay() << ", this);" os << " sim_->thread_delay(" << proc->delay() << ", this);"
<< endl; << endl;
os << " return false;" << endl;
os << " }" << endl; os << " }" << endl;
os << " void step_" << thread_step_ << "_()" << endl; os << " bool step_" << thread_step_ << "_()" << endl;
os << " {" << endl; os << " {" << endl;
proc->emit_proc_recurse(os, this); proc->emit_proc_recurse(os, this);
@ -609,10 +642,11 @@ void target_vvm::proc_delay(ostream&os, const NetPDelay*proc)
void target_vvm::end_process(ostream&os, const NetProcTop*proc) void target_vvm::end_process(ostream&os, const NetProcTop*proc)
{ {
if (proc->type() == NetProcTop::KALWAYS) { if (proc->type() == NetProcTop::KALWAYS) {
os << " step_ = &step_0_;" << endl; os << setw(indent_) << "" << "step_ = &step_0_;" << endl;
os << " step_0_(); // XXXX" << endl; os << setw(indent_) << "" << "return true;" << endl;
} else { } else {
os << " step_ = 0;" << endl; os << setw(indent_) << "" << "step_ = 0;" << endl;
os << setw(indent_) << "" << "return false;" << endl;
} }
os << " }" << endl; os << " }" << endl;
@ -628,6 +662,11 @@ extern const struct target tgt_vvm = {
}; };
/* /*
* $Log: t-vvm.cc,v $ * $Log: t-vvm.cc,v $
* Revision 1.5 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.4 1998/11/09 18:55:34 steve * Revision 1.4 1998/11/09 18:55:34 steve
* Add procedural while loops, * Add procedural while loops,
* Parse procedural for loops, * Parse procedural for loops,

41
vvm/display.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: display.cc,v 1.1 1998/11/09 23:44:10 steve Exp $" #ident "$Id: display.cc,v 1.2 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -28,31 +28,35 @@ static void format_bit(ostream&os, class vvm_calltf_parm*parm)
{ {
switch (parm->type()) { switch (parm->type()) {
case vvm_calltf_parm::NONE: case vvm_calltf_parm::NONE:
cout << "z"; os << "z";
break; break;
case vvm_calltf_parm::ULONG: case vvm_calltf_parm::ULONG:
cout << ((parm->as_ulong()&1) ? "0" : "1"); os << ((parm->as_ulong()&1) ? "0" : "1");
break; break;
case vvm_calltf_parm::STRING: case vvm_calltf_parm::STRING:
cout << parm->as_string(); os << parm->as_string();
break; break;
case vvm_calltf_parm::BITS: case vvm_calltf_parm::BITS:
cout << parm->as_bits()->get_bit(0); os << parm->as_bits()->get_bit(0);
break; break;
} }
} }
static void format_dec(ostream&os, class vvm_calltf_parm*parm) static void format_dec(vvm_simulation*sim, ostream&os,
class vvm_calltf_parm*parm)
{ {
switch (parm->type()) { switch (parm->type()) {
case vvm_calltf_parm::TIME:
os << sim->get_sim_time();
break;
case vvm_calltf_parm::NONE: case vvm_calltf_parm::NONE:
cout << "0"; os << "0";
break; break;
case vvm_calltf_parm::ULONG: case vvm_calltf_parm::ULONG:
cout << parm->as_ulong(); os << parm->as_ulong();
break; break;
case vvm_calltf_parm::STRING: case vvm_calltf_parm::STRING:
cout << parm->as_string(); os << parm->as_string();
break; break;
case vvm_calltf_parm::BITS: { case vvm_calltf_parm::BITS: {
unsigned long val = 0; unsigned long val = 0;
@ -62,7 +66,7 @@ static void format_dec(ostream&os, class vvm_calltf_parm*parm)
if (bstr->get_bit(idx) == V1) val |= mask; if (bstr->get_bit(idx) == V1) val |= mask;
mask <<= 1; mask <<= 1;
} }
cout << val; os << val;
break; break;
} }
} }
@ -71,6 +75,9 @@ static void format_dec(ostream&os, class vvm_calltf_parm*parm)
static void format_name(ostream&os, class vvm_calltf_parm*parm) static void format_name(ostream&os, class vvm_calltf_parm*parm)
{ {
switch (parm->type()) { switch (parm->type()) {
case vvm_calltf_parm::TIME:
os << "$time";
break;
case vvm_calltf_parm::NONE: case vvm_calltf_parm::NONE:
break; break;
case vvm_calltf_parm::ULONG: case vvm_calltf_parm::ULONG:
@ -85,7 +92,8 @@ static void format_name(ostream&os, class vvm_calltf_parm*parm)
} }
} }
static unsigned format(const string&str, unsigned nparms, static unsigned format(vvm_simulation*sim, const string&str,
unsigned nparms,
class vvm_calltf_parm*parms) class vvm_calltf_parm*parms)
{ {
char prev = 0; char prev = 0;
@ -101,7 +109,7 @@ static unsigned format(const string&str, unsigned nparms,
break; break;
case 'd': case 'd':
case 'D': case 'D':
format_dec(cout, parms+next_parm); format_dec(sim, cout, parms+next_parm);
next_parm += 1; next_parm += 1;
break; break;
case 'm': case 'm':
@ -144,8 +152,8 @@ void Sdisplay(vvm_simulation*sim, const string&name,
cout << parms[idx].as_ulong(); cout << parms[idx].as_ulong();
break; break;
case vvm_calltf_parm::STRING: case vvm_calltf_parm::STRING:
idx += format(parms[idx].as_string(), idx += format(sim, parms[idx].as_string(),
nparms-idx-1, parms+idx+1); nparms-idx-1, parms+idx+1);
break; break;
case vvm_calltf_parm::BITS: case vvm_calltf_parm::BITS:
cout << *parms[idx].as_bits(); cout << *parms[idx].as_bits();
@ -198,6 +206,11 @@ void Smonitor(vvm_simulation*sim, const string&name,
/* /*
* $Log: display.cc,v $ * $Log: display.cc,v $
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:10 steve * Revision 1.1 1998/11/09 23:44:10 steve
* Add vvm library. * Add vvm library.
* *

8
vvm/vvm.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm.h,v 1.1 1998/11/09 23:44:10 steve Exp $" #ident "$Id: vvm.h,v 1.2 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include <vector> # include <vector>
@ -81,6 +81,7 @@ class vvm_bits_t {
virtual vvm_bit_t get_bit(unsigned idx) const =0; virtual vvm_bit_t get_bit(unsigned idx) const =0;
}; };
extern ostream& operator << (ostream&os, vvm_bit_t);
extern ostream& operator << (ostream&os, const vvm_bits_t&str); extern ostream& operator << (ostream&os, const vvm_bits_t&str);
/* /*
@ -214,6 +215,11 @@ class vvm_monitor_t {
/* /*
* $Log: vvm.h,v $ * $Log: vvm.h,v $
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:10 steve * Revision 1.1 1998/11/09 23:44:10 steve
* Add vvm library. * Add vvm library.
* *

41
vvm/vvm_bit.cc
View File

@ -17,29 +17,35 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_bit.cc,v 1.1 1998/11/09 23:44:10 steve Exp $" #ident "$Id: vvm_bit.cc,v 1.2 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
ostream& operator << (ostream&os, vvm_bit_t bit)
{
switch (bit) {
case V0:
os << "0";
break;
case V1:
os << "1";
break;
case Vx:
os << "x";
break;
case Vz:
os << "z";
break;
}
return os;
}
ostream& operator << (ostream&os, const vvm_bits_t&str) ostream& operator << (ostream&os, const vvm_bits_t&str)
{ {
os << str.get_width() << "b'"; os << str.get_width() << "b'";
for (unsigned idx = str.get_width() ; idx > 0 ; idx -= 1) for (unsigned idx = str.get_width() ; idx > 0 ; idx -= 1)
switch (str.get_bit(idx)) { os << str.get_bit(idx);
case V0:
os << "0";
break;
case V1:
os << "1";
break;
case Vx:
os << "x";
break;
case Vz:
os << "z";
break;
}
return os; return os;
} }
@ -94,6 +100,11 @@ vvm_bit_t add_with_carry(vvm_bit_t l, vvm_bit_t r, vvm_bit_t&carry)
/* /*
* $Log: vvm_bit.cc,v $ * $Log: vvm_bit.cc,v $
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:10 steve * Revision 1.1 1998/11/09 23:44:10 steve
* Add vvm library. * Add vvm library.
* *

8
vvm/vvm_gates.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_gates.h,v 1.1 1998/11/09 23:44:11 steve Exp $" #ident "$Id: vvm_gates.h,v 1.2 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -205,6 +205,7 @@ class vvm_pevent {
void wait(EDGE, vvm_thread*); void wait(EDGE, vvm_thread*);
void set(vvm_simulation*sim, unsigned, vvm_bit_t val); void set(vvm_simulation*sim, unsigned, vvm_bit_t val);
vvm_bit_t get() const { return value_; }
private: private:
vvm_bit_t value_; vvm_bit_t value_;
@ -218,6 +219,11 @@ class vvm_pevent {
/* /*
* $Log: vvm_gates.h,v $ * $Log: vvm_gates.h,v $
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:11 steve * Revision 1.1 1998/11/09 23:44:11 steve
* Add vvm library. * Add vvm library.
* *

9
vvm/vvm_simulation.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_simulation.cc,v 1.1 1998/11/09 23:44:11 steve Exp $" #ident "$Id: vvm_simulation.cc,v 1.2 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -184,7 +184,7 @@ class delay_event : public vvm_event {
public: public:
delay_event(vvm_thread*thr) : thr_(thr) { } delay_event(vvm_thread*thr) : thr_(thr) { }
void event_function() { thr_->go(); } void event_function() { while (thr_->go()) /* empty */; }
private: private:
vvm_thread*thr_; vvm_thread*thr_;
}; };
@ -210,6 +210,11 @@ void vvm_simulation::thread_active(vvm_thread*thr)
/* /*
* $Log: vvm_simulation.cc,v $ * $Log: vvm_simulation.cc,v $
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:11 steve * Revision 1.1 1998/11/09 23:44:11 steve
* Add vvm library. * Add vvm library.
* *

13
vvm/vvm_thread.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_thread.h,v 1.1 1998/11/09 23:44:11 steve Exp $" #ident "$Id: vvm_thread.h,v 1.2 1998/11/10 00:48:31 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -38,7 +38,11 @@ class vvm_thread {
public: public:
explicit vvm_thread(vvm_simulation*sim); explicit vvm_thread(vvm_simulation*sim);
virtual ~vvm_thread(); virtual ~vvm_thread();
virtual void go() =0;
// This method executes a setp of the thread. The engine will
// continue to call go as long as it returns true. The thread
// will return false if it is ready to give up the CPU.
virtual bool go() =0;
protected: protected:
vvm_simulation*const sim_; vvm_simulation*const sim_;
@ -46,6 +50,11 @@ class vvm_thread {
/* /*
* $Log: vvm_thread.h,v $ * $Log: vvm_thread.h,v $
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:11 steve * Revision 1.1 1998/11/09 23:44:11 steve
* Add vvm library. * Add vvm library.
* *