Add regression tests for shadowing type identifiers

Check that visible type identifiers can be shadowed by declarations in
other namespaces or nested scopes. Keep each grammar category in a
separate regression so failures identify the affected rule.

Also check that package import and export items can name a type
identifier.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

ivtest/ivltests/sv_type_identifier_ams_name_fields.v

@@ -0,0 +1,18 @@
+// Check that nature name fields can shadow visible type identifiers.
+
+typedef int ACCESS_NAME;
+typedef int IDT_NAME;
+typedef int DDT_NAME;
+
+nature type_id_nature;
+  units = "V";
+  access = ACCESS_NAME;
+  idt_nature = IDT_NAME;
+  ddt_nature = DDT_NAME;
+endnature
+
+module test;
+  initial begin
+    $display("PASSED");
+  end
+endmodule

ivtest/ivltests/sv_type_identifier_config_name.v

@@ -0,0 +1,13 @@
+// Check that a config name can shadow a visible type identifier.
+
+typedef int CFG_NAME;
+
+config CFG_NAME;
+  design test;
+endconfig
+
+module test;
+  initial begin
+    $display("PASSED");
+  end
+endmodule

ivtest/ivltests/sv_type_identifier_foreach_name.v

@@ -0,0 +1,29 @@
+// Check that foreach loop variables can shadow visible type identifiers.
+
+typedef int I;
+typedef int J;
+
+module test;
+
+  reg failed;
+  int array [2][2];
+
+  initial begin
+    failed = 1'b0;
+
+    foreach (array[I,J]) begin
+      array[I][J] = I * 10 + J;
+    end
+
+    if (array[0][0] != 0 || array[0][1] != 1 ||
+        array[1][0] != 10 || array[1][1] != 11) begin
+      $display("FAILED(%0d). foreach indices did not hide typedefs", `__LINE__);
+      failed = 1'b1;
+    end
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+
+endmodule

ivtest/ivltests/sv_type_identifier_genvar_name.v

@@ -0,0 +1,27 @@
+// Check that a genvar name can shadow a visible type identifier.
+
+typedef int G;
+
+module test;
+  reg failed;
+
+  genvar G;
+  generate
+    for (G = 0; G < 2; G = G + 1) begin : gen_block
+      localparam int VALUE = G;
+    end
+  endgenerate
+
+  initial begin
+    failed = 1'b0;
+
+    if (gen_block[0].VALUE != 0 || gen_block[1].VALUE != 1) begin
+      $display("FAILED(%0d). genvar name did not hide typedef", `__LINE__);
+      failed = 1'b1;
+    end
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+endmodule

ivtest/ivltests/sv_type_identifier_modport_name.v

@@ -0,0 +1,19 @@
+// Check that a modport name can shadow a visible type identifier.
+
+typedef int M;
+
+interface type_id_modport_ifc;
+  logic value;
+
+  modport M(input value);
+endinterface
+
+module test;
+
+  type_id_modport_ifc i_ifc();
+
+  initial begin
+    $display("PASSED");
+  end
+
+endmodule

ivtest/ivltests/sv_type_identifier_module_name.v

@@ -0,0 +1,17 @@
+// Check that a module name can shadow a visible type identifier.
+
+package p;
+  typedef int M;
+endpackage
+
+import p::*;
+
+module M;
+  initial begin
+    $display("PASSED");
+  end
+endmodule
+
+module test;
+  M i();
+endmodule

ivtest/ivltests/sv_type_identifier_package_item.v

@@ -0,0 +1,31 @@
+// Check that package import and export items can name a type identifier.
+
+package type_id_name_pkg;
+  typedef logic [3:0] T;
+endpackage
+
+package type_id_name_export_pkg;
+  import type_id_name_pkg::T;
+  export type_id_name_pkg::T;
+endpackage
+
+module test;
+  import type_id_name_export_pkg::T;
+
+  reg failed;
+  T value;
+
+  initial begin
+    failed = 1'b0;
+    value = 4'ha;
+
+    if ($bits(value) != 4 || value != 4'ha) begin
+      $display("FAILED(%0d). Imported type mismatch", `__LINE__);
+      failed = 1'b1;
+    end
+
+    if (!failed) begin
+      $display("PASSED");
+    end
+  end
+endmodule

ivtest/ivltests/sv_type_identifier_specparam_name.v

@@ -0,0 +1,14 @@
+// Check that a specparam name can shadow a visible type identifier.
+
+typedef int SP_DELAY;
+
+module test(input in, output out);
+  specify
+    specparam SP_DELAY = 1;
+    (in => out) = SP_DELAY;
+  endspecify
+
+  initial begin
+    $display("PASSED");
+  end
+endmodule

ivtest/regress-vvp.list

@@ -378,6 +378,14 @@ sv_string_method_substr_too_few_arg_fail	vvp_tests/sv_string_method_substr_too_f
 sv_soft_packed_union		vvp_tests/sv_soft_packed_union.json
 sv_soft_packed_union_fail1	vvp_tests/sv_soft_packed_union_fail1.json
 sv_super_member_fail		vvp_tests/sv_super_member_fail.json
+sv_type_identifier_ams_name_fields	vvp_tests/sv_type_identifier_ams_name_fields.json
+sv_type_identifier_config_name	vvp_tests/sv_type_identifier_config_name.json
+sv_type_identifier_foreach_name	vvp_tests/sv_type_identifier_foreach_name.json
+sv_type_identifier_genvar_name	vvp_tests/sv_type_identifier_genvar_name.json
+sv_type_identifier_modport_name	vvp_tests/sv_type_identifier_modport_name.json
+sv_type_identifier_module_name	vvp_tests/sv_type_identifier_module_name.json
+sv_type_identifier_package_item	vvp_tests/sv_type_identifier_package_item.json
+sv_type_identifier_specparam_name	vvp_tests/sv_type_identifier_specparam_name.json
 sv_type_param_restrict_class1	vvp_tests/sv_type_param_restrict_class1.json
 sv_type_param_restrict_class2	vvp_tests/sv_type_param_restrict_class2.json
 sv_type_param_restrict_class_fail1	vvp_tests/sv_type_param_restrict_class_fail1.json

ivtest/vvp_tests/sv_type_identifier_ams_name_fields.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_ams_name_fields.v",
+    "iverilog-args" : [ "-g2005-sv", "-gverilog-ams" ]
+}

ivtest/vvp_tests/sv_type_identifier_config_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_config_name.v",
+    "iverilog-args" : [ "-g2005-sv", "-gverilog-ams" ]
+}

ivtest/vvp_tests/sv_type_identifier_foreach_name.json

@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_foreach_name.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment"     : "Typedefs and foreach loops are SystemVerilog",
+        "type"          : "CE"
+    }
+}

ivtest/vvp_tests/sv_type_identifier_genvar_name.json

@@ -0,0 +1,9 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_genvar_name.v",
+    "iverilog-args" : [ "-g2005-sv" ],
+    "vlog95" : {
+        "__comment"     : "Typedefs and generate blocks are SystemVerilog",
+        "type"          : "CE"
+    }
+}

ivtest/vvp_tests/sv_type_identifier_modport_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_modport_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_module_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_module_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_package_item.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_package_item.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}

ivtest/vvp_tests/sv_type_identifier_specparam_name.json

@@ -0,0 +1,5 @@
+{
+    "type"          : "normal",
+    "source"        : "sv_type_identifier_specparam_name.v",
+    "iverilog-args" : [ "-g2005-sv" ]
+}