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Spelling fixes 

Mostly comments, but a few format strings
This commit is contained in:
Larry Doolittle 2011-03-04 13:52:08 -08:00 committed by Stephen Williams
parent 09664bc52e
commit 76103f2167
58 changed files with 120 additions and 120 deletions
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10
BUGS.txt
View File

@ -53,7 +53,7 @@ So, if your program doesn't compile, tell me so, tell me where the
error occurs, and include a complete Perfectly Valid Test Program(tm).
You tell me that it fails to compile for you, and I find that it
compiles for me, then hooray I fixed it. It can happen, you
know. What's on my disk is more recent then the latest snapshot.
know. What's on my disk is more recent than the latest snapshot.
If your program does compile, but generates incorrect output, I need
to know what it says and what you think it should say. From this I can
@ -76,13 +76,13 @@ In this case, if possible include not only the sample verilog program,
but the generated netlist file(s) and a clear indication of what went
wrong. If it is not clear to me, I will ask for clarification.
* The Output is Correct, But Less Then Ideal
* The Output is Correct, But Less Than Ideal
If the output is strictly correct, but just not good enough for
practical use, I would like to know. These sorts of problems are
likely to be more subjective then a core dump, but are worthy of
likely to be more subjective than a core dump, but are worthy of
consideration. However, realize that outright errors will get more
attention then missed optimizations.
attention than missed optimizations.
THE MAKING OF A GOOD TEST PROGRAM
@ -104,7 +104,7 @@ module may not be needed as long as the ``-s <name>'' switch is
given.
So when you send a test case, ask yourself "Can poor overworked Steve
invoke the error without any Verilog other then what is included?" And
invoke the error without any Verilog other than what is included?" And
while we are at it, please place a copyright notice in your test
program and include a GPL license statement if you can. Your test
program may find its way into the test suite, and the notices will

2
Makefile.in
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@ -21,7 +21,7 @@ SHELL = /bin/sh
# This string is used as an installation suffix. It modifies certain
# key install paths/files such that a build and install of Icarus Verilog
# with the same $(prefix) but a different $(suffix) will not interfere.
# The normal configuratin leaves suffix empty
# The normal configuration leaves suffix empty
suffix = @install_suffix@
prefix = @prefix@

2
cprop.cc
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@ -885,7 +885,7 @@ void cprop_functor::lpm_mux(Design*des, NetMux*obj)
/* Otherwise, we cannot accurately do a substitution. If
one input is non-constant, then that input may have a
HiZ value, and there is no Verilog logic other then a
HiZ value, and there is no Verilog logic other than a
MUX that can pass a HiZ value. */
flag = false;
}

4
driver/globals.h
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@ -28,10 +28,10 @@ extern const char*base;
extern char* iconfig_path;
extern char* iconfig_common_path;
/* Ths is the optional -M<dependfile> value, if one was supplied. */
/* This is the optional -M<dependfile> value, if one was supplied. */
extern const char*depfile;
/* Ths is the optional -N<path> value, if one was supplied. */
/* This is the optional -N<path> value, if one was supplied. */
extern const char*npath;
/* This is the name of the output file that the user selected. */

2
driver/iverilog.man
View File

@ -184,7 +184,7 @@ implies the synthesis \fB-S\fP flag.
.SH "WARNING TYPES"
These are the types of warnings that can be selected by the \fB-W\fP
switch. All the warning types (other then \fBall\fP) can also be
switch. All the warning types (other than \fBall\fP) can also be
prefixed with \fBno-\fP to turn off that warning. This is most useful
after a \fB-Wall\fP argument to suppress isolated warning types.

2
elab_anet.cc
View File

@ -81,7 +81,7 @@ NetNet* PEConcat::elaborate_anet(Design*des, NetScope*scope) const
concat operator from least significant to most significant,
which is opposite from how they are given in the list.
Allow for a repeat count other then 1 by repeating the
Allow for a repeat count other than 1 by repeating the
connect loop as many times as necessary. */
NetNet*osig = new NetNet(scope, scope->local_symbol(),

20
elab_net.cc
View File

@ -192,7 +192,7 @@ NetNet* PEBinary::elaborate_net_add_(Design*des, NetScope*scope,
/* The owidth is the output width of the lpm_add_sub
device. If the desired width is greater then the width of
device. If the desired width is greater than the width of
the operands, then widen the adder and let code below pad
the operands. If this is an adder, we can take advantage of
the carry bit. */
@ -735,7 +735,7 @@ NetNet* PEBinary::elaborate_net_cmp_(Design*des, NetScope*scope,
/*
* Elaborate a divider gate. This function create a NetDivide gate
* which has exactly the right sized DataA, DataB and Result ports. If
* the l-value is wider then the result, then pad.
* the l-value is wider than the result, then pad.
*/
NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
unsigned lwidth,
@ -789,7 +789,7 @@ NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
// Make an output signal that is the width of the l-value.
// Due to above calculation of rwidth, we know that the result
// will be no more then the l-value, so it is safe to connect
// will be no more than the l-value, so it is safe to connect
// all the result pins to the osig.
NetNet*osig = new NetNet(scope, scope->local_symbol(),
@ -801,7 +801,7 @@ NetNet* PEBinary::elaborate_net_div_(Design*des, NetScope*scope,
connect(div->pin_Result(idx), osig->pin(idx));
// If the lvalue is larger then the result, then pad the
// If the lvalue is larger than the result, then pad the
// output with constant 0. This can happen for example in
// cases like this:
// wire [3;0] a, b;
@ -859,7 +859,7 @@ NetNet* PEBinary::elaborate_net_mod_(Design*des, NetScope*scope,
for (unsigned idx = 0 ; idx < cnt ; idx += 1)
connect(mod->pin_Result(idx), osig->pin(idx));
/* If the lvalue is larger then the result, then pad the
/* If the lvalue is larger than the result, then pad the
output with constant 0. */
if (cnt < osig->pin_count()) {
NetConst*tmp = new NetConst(scope, scope->local_symbol(),
@ -1030,7 +1030,7 @@ NetNet* PEBinary::elaborate_net_mul_(Design*des, NetScope*scope,
for (unsigned idx = 0 ; idx < cnt ; idx += 1)
connect(mult->pin_Result(idx), osig->pin(idx));
/* If the lvalue is larger then the result, then pad the
/* If the lvalue is larger than the result, then pad the
output with constant 0. */
if (cnt < osig->pin_count()) {
NetConst*tmp = new NetConst(scope, scope->local_symbol(),
@ -1235,7 +1235,7 @@ NetNet* PECallFunction::elaborate_net(Design*des, NetScope*scope,
NetScope*dscope = def->scope();
assert(dscope);
/* This must be a ufuction that returns a signal. */
/* This must be a function that returns a signal. */
assert(def->return_sig());
/* check the validity of the parameters. */
@ -1418,7 +1418,7 @@ NetNet* PEConcat::elaborate_net(Design*des, NetScope*scope,
concat operator from least significant to most significant,
which is opposite from how they are given in the list.
Allow for a repeat count other then 1 by repeating the
Allow for a repeat count other than 1 by repeating the
connect loop as many times as necessary. */
NetNet*osig = new NetNet(scope, scope->local_symbol(),
@ -1634,7 +1634,7 @@ NetNet* PEIdent::elaborate_net(Design*des, NetScope*scope,
with the sig type.
Be careful to check the bit ordering. If the msb is
less significant then the msb, then the source is
less significant than the msb, then the source is
broken. I can hack it in order to go on, but report
an error. */
@ -2273,7 +2273,7 @@ NetNet* PETernary::elaborate_net(Design*des, NetScope*scope,
assert(expr_sig->pin_count() == 1);
/* This is the width of the LPM_MUX device that I'm about to
create. It may be smaller then the desired output, but I'll
create. It may be smaller than the desired output, but I'll
handle padding below.
Create a NetNet object wide enough to hold the

2
elab_scope.cc
View File

@ -243,7 +243,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope) const
}
// Scan through all the named events in this scope. We do not
// need anything more then the current scope to do this
// need anything more than the current scope to do this
// elaboration, so do it now. This allows for normal
// elaboration to reference these events.

8
elaborate.cc
View File

@ -257,7 +257,7 @@ void PGAssign::elaborate(Design*des, NetScope*scope) const
assert(lval && rval);
/* If the r-value insists on being smaller then the l-value
/* If the r-value insists on being smaller than the l-value
(perhaps it is explicitly sized) the pad it out to be the
right width so that something is connected to all the bits
of the l-value. */
@ -286,7 +286,7 @@ void PGBuiltin::elaborate(Design*des, NetScope*scope) const
name = scope->local_symbol();
/* If the Verilog source has a range specification for the
gates, then I am expected to make more then one
gates, then I am expected to make more than one
gate. Figure out how many are desired. */
if (msb_) {
NetExpr*msb_exp = elab_and_eval(des, scope, msb_);
@ -1640,7 +1640,7 @@ NetProc* PCondit::elaborate(Design*des, NetScope*scope) const
}
}
// If the condition expression is more then 1 bits, then
// If the condition expression is more than 1 bits, then
// generate a comparison operator to get the result down to
// one bit. Turn <e> into <e> != 0;
@ -2260,7 +2260,7 @@ NetProc* PEventStatement::elaborate_wait(Design*des, NetScope*scope,
return 0;
}
// If the condition expression is more then 1 bits, then
// If the condition expression is more than 1 bits, then
// generate a reduction operator to get the result down to
// one bit. In other words, Turn <e> into |<e>;

2
eval_tree.cc
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@ -686,7 +686,7 @@ NetEConst* NetEBComp::eval_tree()
case '<': // Less than
return eval_less_();
case '>': // Greater then
case '>': // Greater than
return eval_gt_();
default:

6
examples/pal_reg.v
View File

@ -26,7 +26,7 @@
* iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v
*
* The output file name (passed through the -o<file> switch) can be
* any file you desire. If the compilation and fittin all succeed, the
* any file you desire. If the compilation and fitting all succeed, the
* output file will be a JEDEC file that you can take to your favorite
* PROM programmer to program the part.
*
@ -45,7 +45,7 @@
*
* The output drivers are controlled by a single active low output
* enable. I used bufif0 devices in this example, but the exact same
* thing can be achived with a continuous assignment like so:
* thing can be achieved with a continuous assignment like so:
*
* assign out = oe? 8'hzz : Q;
*
@ -76,7 +76,7 @@ endmodule
* a PLCC package.
*
* Note that this module has no logic in it. It is a convention I use
* that I put all the functionality in a seperate module (seen above)
* that I put all the functionality in a separate module (seen above)
* and isolate the Icarus Verilog specific $attribute madness into a
* top-level module. The advantage of this style is that the entire
* module can be `ifdef'ed out when doing simulation and you don't

2
examples/show_vcd.vl
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@ -63,7 +63,7 @@
*
* The $dumpvars task tells the simulation what variables to write to
* the VCD output. The first parameter is how far to descend while
* scanning a scope, and the remaining paramters are signals or scope
* scanning a scope, and the remaining parameters are signals or scope
* names to include in the dump. If a scope name is given, all the
* signals within the scope are dumped. If a wire or register name is
* given, that signal is included.

12
examples/sqrt-virtex.v
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@ -20,7 +20,7 @@
*/
/*
* This module is a synthesizeable square-root function. It is also a
* This module is a synthesizable square-root function. It is also a
* detailed example of how to target Xilinx Virtex parts using
* Icarus Verilog. In fact, for no particular reason other than to
* be excessively specific, I will step through the process of
@ -30,7 +30,7 @@
* In addition to Icarus Verilog, you will need implementation
* software from Xilinx. As of this writing, this example was tested
* with Foundation 4.2i, but it should work the same with ISE and
* Webpack software.
* WebPACK software.
*
* This example source contains all the Verilog needed to do
* everything described below. We use conditional compilation to
@ -55,7 +55,7 @@
* "PASSED" and finishes the simulation.
*
* When you take a close look at the "main" module below, you will see
* that it uses Verilog constructs that are not synthesizeable. This
* that it uses Verilog constructs that are not synthesizable. This
* is fine, as we will never try to synthesize it.
*
* LIBRARY PARTS
@ -78,7 +78,7 @@
* Without any preprocessor directives, the only module is the sqrt32
* module, so sqrt32 is compiled as the root. The ports of the module
* are automatically made into ports of the sqrt32.edf netlist, and
* the contents of the sqrt32 module are connected approprately.
* the contents of the sqrt32 module are connected appropriately.
*
* COMPLETE CHIP DESIGNS
*
@ -154,7 +154,7 @@
*
* The POST_MAP compiler directive causes the GSR manipulations
* included in the test bench to be compiled in, to simulate the chip
* startup. Other then that, the test bench runs the post-map design
* startup. Other than that, the test bench runs the post-map design
* the same way the pre-synthesis design works.
*
* Run this design with the command:
@ -183,7 +183,7 @@
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32bit numbers, this will never run more then 16 iterations,
* For 32bit numbers, this will never run more than 16 iterations,
* which amounts to 16 clocks.
*/

2
examples/sqrt.vl
View File

@ -50,7 +50,7 @@
* where sqrt(y) is the exact square root of y and floor(N) is the
* largest integer <= N.
*
* For 32bit numbers, this will never run more then 16 iterations,
* For 32bit numbers, this will never run more than 16 iterations,
* which amounts to 16 clocks.
*/

6
ieee1364-notes.txt
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@ -249,7 +249,7 @@ exactly the same so far as the compiler is concerned.
Unfortunately, Cadence seems to feel otherwise. In particular, it has
been reported that although {1'b0, 16} causes an error, {1'b0, 15+1}
is accepted. Further testing shows that any expression other then a
is accepted. Further testing shows that any expression other than a
simple unsized constant is accepted there, even if all the operands of
all the operators that make up the expression are unsized integers.
@ -282,12 +282,12 @@ One might note that the quote from section 4.1.14 says "Unsized
expressions...", so arguably accepting (15+1) or even (16+0) as an
operand to a concatenation is not a violation of the letter of the
law. However, the very next sentence of the quote expresses the
intent, and accepting (15+1) as having a more defined size then (16)
intent, and accepting (15+1) as having a more defined size than (16)
seems to be a violation of that intent.
Whatever a compiler decides the size is, the user has no way to
predict it, and the compiler should not have the right to treat (15+1)
any differently then (16). Therefore, Icarus Verilog takes the
any differently than (16). Therefore, Icarus Verilog takes the
position that such expressions are *unsized* and are not allowed as
operands to concatenations. Icarus Verilog will in general assume that
operations on unsized numbers produce unsized results. There are

6
ivl_target.h
View File

@ -650,7 +650,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* ivl_lpm_decode
* Return the DECODER associated with this LPM_FF device. The
* decoder for a FF takes an input address and generates an enable
* input for no more then 1 bit (can be none) of the FF device.
* input for no more than 1 bit (can be none) of the FF device.
*
* ivl_lpm_q
* Return the output data nexus for device types that have a single
@ -985,7 +985,7 @@ extern ivl_expr_t ivl_parameter_expr(ivl_parameter_t net);
* ivl_scope_children
* A scope may in turn contain other scopes. This method iterates
* through all the child scopes of a given scope. If the function
* returns any value other then 0, the iteration stops and the
* returns any value other than 0, the iteration stops and the
* method returns that value. Otherwise, iteration continues until
* the children run out.
*
@ -1212,7 +1212,7 @@ extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net);
/*
* The following functions retrieve specific single values from the
* statement. These values are the bits of data and parameters that
* make up the statement. Many of these functions apply to more then
* make up the statement. Many of these functions apply to more than
* one type of statement, so the comment in front of them tells which
* statement types can be passed to the function.
*

2
ivlpp/lexor.lex
View File

@ -593,7 +593,7 @@ static void do_define()
}
/* Detect the continuation sequence. If I find it, remove it
and the white space that preceeds it, then replace all that
and the white space that precedes it, then replace all that
with a single newline. */
if ((cp > yytext) && (cp[-1] == '\\')) {

2
lexor.lex
View File

@ -681,7 +681,7 @@ static verinum*make_unsized_dec(const char*ptr)
if (ptr[0] == '\'') {
/* The number has decorations of the form 'sd<digits>,
possibly with space between the d and the <digits>.
Also, the 's' is optional, and markes the number as
Also, the 's' is optional, and marks the number as
signed. */
ptr += 1;

2
libveriuser/a_next.c
View File

@ -49,7 +49,7 @@ handle acc_next(PLI_INT32 *type, handle scope, handle prev)
/*
* The acc_next_* functions need to be reentrant, so we need to
* rescan all the items upto the previous one, then return
* rescan all the items up to the previous one, then return
* the next one.
*/
iter = vpi_iterate(vpiScope, scope); // ICARUS extension

2
libveriuser/getcstringp.c
View File

@ -21,7 +21,7 @@
#include <acc_user.h>
/*
* tf_getinstance implemented using equvalent acc_ routing
* tf_getinstance implemented using equivalent acc_ routing
*/
char *tf_getcstringp(int n)
{

2
libveriuser/priv.h
View File

@ -29,7 +29,7 @@
extern char* __acc_newstring(const char*txt);
/*
* Trace file for loggint ACC and TF calls.
* Trace file for logging ACC and TF calls.
*/
FILE* pli_trace;

2
libveriuser/veriusertfs.c
View File

@ -20,7 +20,7 @@
/*
* Contains the routines required to implement veriusertfs routines
* via VPI. This is extremly ugly, so don't look after eating dinner.
* via VPI. This is extremely ugly, so don't look after eating dinner.
*/
# include <string.h>

2
main.cc
View File

@ -662,7 +662,7 @@ int main(int argc, char*argv[])
des->set_flags(flags);
/* Done iwth all the pform data. Delete the modules. */
/* Done with all the pform data. Delete the modules. */
for (map<perm_string,Module*>::iterator idx = pform_modules.begin()
; idx != pform_modules.end() ; idx ++) {

6
mingw.txt
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@ -71,7 +71,7 @@ The msys package is available from the mingw download site. This is
not the compiler but a collection of *nix tools ported to Windows and
wrapped in a convenient installer. The msys package is all the various
basic tools (shells, file utils, etc) and the msysDTK is extra
developer tools other then the compiler.
developer tools other than the compiler.
Download the msys-1.x.x.exe and msysdtc-1.x.x.exe binaries. These are
self-installing packages. Install msys first, and then msysDTC. Most
@ -91,7 +91,7 @@ commands below.
The obvious step 2, then, is install the mingw compilers. These can be
found at the web page <http://www.mingw.org>. The Mingw-5.x.x package
is a convenient remote installer. Download this program and run
it. The installer will ask wich components you want to install. You
it. The installer will ask which components you want to install. You
need only the base C compiler and the C++ compiler. (You may install
other languages if you wish.)
@ -150,7 +150,7 @@ You will need these gnuwin32 packages to compile Icarus Verilog:
I suggest creating a common directory for holding all your gnuwin32
packages. I use C:\gnuwin32. The download page at the gnuwin32 site
has a "setup" link for each of these packages. Click the setup to
download the installer for each of the desired programes, then execute
download the installer for each of the desired programs, then execute
the downloaded .exe files to invoke the installer. Install into the
c:\gunwin32 directory.

2
net_nex_input.cc
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@ -208,7 +208,7 @@ NexusSet* NetAssignBase::nex_input(bool rem_out)
{
NexusSet*result = rval_->nex_input(rem_out);
/* It is possible that the lval_ can hav nex_input values. In
/* It is possible that the lval_ can have nex_input values. In
particular, index expressions are statement inputs as well,
so should be addressed here. */
for (NetAssign_*cur = lval_ ; cur ; cur = cur->more) {

2
net_nex_output.cc
View File

@ -149,7 +149,7 @@ void NetPDelay::nex_output(NexusSet&out)
/*
* For the purposes of synthesis, system task calls have no output at
* all. This is OK because most system tasks are not synthesizeable in
* all. This is OK because most system tasks are not synthesizable in
* the first place.
*/
void NetSTask::nex_output(NexusSet&out)

18
netlist.h
View File

@ -548,7 +548,7 @@ class NetCLShift : public NetNode {
* This class supports the LPM_COMPARE device.
*
* The width of the device is the width of the inputs. If one of the
* inputs is narrower then the other, it is up to the generator to
* inputs is narrower than the other, it is up to the generator to
* make sure all the data pins are properly driven.
*
* NOTE: This is not the same as the device used to support case
@ -919,7 +919,7 @@ class NetMemory {
* EDIF LPM Version 2 1 0 standard. It is used as a structural
* implementation of the * operator. The device has inputs DataA and
* DataB that can have independent widths, as can the result. If the
* result is smaller then the widths of a and b together, then the
* result is smaller than the widths of a and b together, then the
* device drops the least significant bits of the product.
*/
class NetMult : public NetNode {
@ -1389,7 +1389,7 @@ class NetLogic : public NetNode {
/*
* The UDP is a User Defined Primitive from the Verilog source. Do not
* expand it out any further then this in the netlist, as this can be
* expand it out any further than this in the netlist, as this can be
* used to represent target device primitives.
*
* The UDP can be combinational or sequential. The sequential UDP
@ -1411,7 +1411,7 @@ class NetLogic : public NetNode {
* N -- (1x)
*
* It also takes one of the following glob letters to represent more
* then one item.
* than one item.
*
* p -- 01, 0x or x1 // check this with the lexer
* n -- 10, 1x or x0 // check this with the lexer
@ -1424,7 +1424,7 @@ class NetLogic : public NetNode {
* SEQUENTIAL
* These objects have a single bit of memory. The logic table includes
* an entry for the current value, and allows edges on the inputs. In
* canonical form, inly then entries that generate 0, 1 or - (no change)
* canonical form, only the entries that generate 0, 1 or - (no change)
* are listed.
*
* COMBINATIONAL
@ -2596,8 +2596,8 @@ class NetProcTop : public LineInfo, public Attrib {
* % -- Arithmetic modulus
* & -- Bit-wise AND
* | -- Bit-wise OR
* < -- Less then
* > -- Greater then
* < -- Less than
* > -- Greater than
* e -- Logical equality (==)
* E -- Case equality (===)
* L -- Less or equal
@ -2717,8 +2717,8 @@ class NetEBBits : public NetEBinary {
* this case the bit width of the expression is 1 bit, and the
* operands take their natural widths. The supported operators are:
*
* < -- Less then
* > -- Greater then
* < -- Less than
* > -- Greater than
* e -- Logical equality (==)
* E -- Case equality (===)
* L -- Less or equal (<=)

2
parse.y
View File

@ -1548,7 +1548,7 @@ module_port_list_opt
| { $$ = 0; }
;
/* Module declarations include optional ANSII style module parameter
/* Module declarations include optional ANSI style module parameter
ports. These are simply advance ways to declare parameters, so
that the port declarations may use them. */
module_parameter_port_list_opt

2
pform.cc
View File

@ -365,7 +365,7 @@ static void process_udp_table(PUdp*udp, list<string>*table,
placed in the PUdp object.
The table strings are made up by the parser to be two or
three substrings seperated by ';', i.e.:
three substrings separated by ';', i.e.:
0101:1:1 (synchronous device entry)
0101:0 (combinational device entry)

8
synth2.cc
View File

@ -871,7 +871,7 @@ bool NetCase::synth_async(Design*des, NetScope*scope, bool sync_flag,
/* If after all this is an unspecified case, then get the
input from the synchronous output. Note that we know
by design that there is no relevent default or accum
by design that there is no relevant default or accum
input to use here, as those cases are handled above. */
if (statement_map[item] == 0) {
@ -2076,7 +2076,7 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope,
/* XXXX I really should find a way to check that the
edge used on the reset input is correct. This would
involve interpreting the exression that is fed by the
involve interpreting the expression that is fed by the
reset expression. */
//assert(ev->edge() == NetEvProbe::POSEDGE);
@ -2231,7 +2231,7 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope,
}
/* Detect the case that this is a *synchronous* set/reset. It
is not asyncronous because we know the condition is not
is not asynchronous because we know the condition is not
included in the sensitivity list, but if the if_ case is
constant (has no inputs) then we can model this as a
synchronous set/reset.
@ -2402,7 +2402,7 @@ bool NetEvWait::synth_sync(Design*des, NetScope*scope,
<< endl;
}
/* This can't be other then one unless there are named events,
/* This can't be other than one unless there are named events,
which I cannot synthesize. */
assert(nevents_ == 1);
NetEvent*ev = events_[0];

2
tgt-edif/device.h
View File

@ -77,7 +77,7 @@ struct device_s {
* Return the device_t cookie given the name of the architecture. If
* the device is not found, return 0.
*
* This function is used if the user specifies the archetecture
* This function is used if the user specifies the architecture
* explicitly, with the -parch=name flag.
*/
extern device_t device_from_arch(const char*arch);

2
tgt-fpga/device.h
View File

@ -69,7 +69,7 @@ struct device_s {
* Return the device_t cookie given the name of the architecture. If
* the device is not found, return 0.
*
* This function is used if the user specifies the archetecture
* This function is used if the user specifies the architecture
* explicitly, with the -parch=name flag.
*/
extern device_t device_from_arch(const char*arch);

2
tgt-fpga/iverilog-fpga.man
View File

@ -160,7 +160,7 @@ device pins are connected.
.SH EXAMPLES
.TB 8
.I COMPILING WITH XILINX FOUNDATION/iSE
.I COMPILING WITH XILINX FOUNDATION/ISE
Compile a single-file design with command line tools like so:
.nf

2
verinum.cc
View File

@ -212,7 +212,7 @@ unsigned long verinum::as_ulong() const
*
* If the value is undefined, return 0.
*
* This function presumes that the native format is 2s compliment
* This function presumes that the native format is 2s complement
* (pretty safe these days) and masks/sets bits accordingly. If the
* value is too large for the native form, it truncates the high bits.
*/

2
vpi/lxt2_write.h
View File

@ -279,7 +279,7 @@ struct lxt2_wr_symbol * lxt2_wr_symbol_add(struct lxt2_wr_trace *lt, const char
struct lxt2_wr_symbol * lxt2_wr_symbol_alias(struct lxt2_wr_trace *lt, const char *existing_name, const char *alias, int msb, int lsb);
void lxt2_wr_symbol_bracket_stripping(struct lxt2_wr_trace *lt, int doit);
/* each granule is LXT2_WR_GRANULE_SIZE (32 or 64) timesteps, default is 256 per section */
/* each granule is LXT2_WR_GRANULE_SIZE (32 or 64) time steps, default is 256 per section */
void lxt2_wr_set_maxgranule(struct lxt2_wr_trace *lt, unsigned int maxgranule);
/* time ops */

8
vpi/sys_display.c
View File

@ -184,7 +184,7 @@ static void format_time(unsigned mcd, int fsize,
/* This is the number of characters to the right of the
decimal point. This is defined completely by the
timeformat. It is legal for the precision to be larger then
timeformat. It is legal for the precision to be larger than
the units, and in this case there will be no fraction_chars
at all. */
fraction_chars = timeformat_info.units - format_precision;
@ -193,7 +193,7 @@ static void format_time(unsigned mcd, int fsize,
/* This is the number of zeros I must add to the value to get
the desired precision within the fraction. If this value is
greater then 0, the value does not have enough characters,
greater than 0, the value does not have enough characters,
so I will be adding zeros. */
fraction_pad = time_units - format_precision;
@ -213,7 +213,7 @@ static void format_time(unsigned mcd, int fsize,
/* This is the number of zeros that I must add to the integer
part of the output string to pad the value out to the
desired units. This will only have a non-zero value if the
units of the value is greater then the desired units.
units of the value is greater than the desired units.
Detect the special case where the value is 0. In this case,
do not do any integer filling ever. The output should be
@ -1117,7 +1117,7 @@ static PLI_INT32 sys_monitor_calltf(char*name)
vpiHandle scope = vpi_handle(vpiScope, sys);
vpiHandle argv = vpi_iterate(vpiArgument, sys);
/* If there was a previous $monitor, then remove the calbacks
/* If there was a previous $monitor, then remove the callbacks
related to it. */
if (monitor_callbacks) {
for (idx = 0 ; idx < monitor_info.nitems ; idx += 1)

2
vpi/sys_lxt.c
View File

@ -24,7 +24,7 @@
/*
* This file contains the implementations of the VCD related
* funcitons.
* functions.
*/
# include "vpi_user.h"

2
vpi/sys_lxt2.c
View File

@ -24,7 +24,7 @@
/*
* This file contains the implementations of the VCD related
* funcitons.
* functions.
*/
# include "vpi_user.h"

4
vpi/sys_random.c
View File

@ -52,7 +52,7 @@ long rtl_dist_poisson(long*seed, long mean)
return 0;
}
/* copied from IEEE1364-2001, with slight midifications for 64bit machines. */
/* copied from IEEE1364-2001, with slight modifications for 64bit machines. */
long rtl_dist_uniform(long*seed, long start, long end)
{
double r;
@ -175,7 +175,7 @@ static double uniform(long *seed, long start, long end )
return c;
}
/* copied from IEEE1364-2001, with slight midifications for 64bit machines. */
/* copied from IEEE1364-2001, with slight modifications for 64bit machines. */
static long poisson(long*seed, long mean)
{
long n;

2
vpi/sys_random_mti.c
View File

@ -143,7 +143,7 @@ static PLI_INT32 sys_mti_random_calltf(char*name)
context->mti = NP1;
assert(context);
/* squrrel away context */
/* squirrel away context */
vpi_put_userdata(call_handle, (void *)context);
}

10
vpi/sys_readmem.c
View File

@ -180,7 +180,7 @@ static PLI_INT32 sys_readmem_calltf(char*name)
return 0;
}
/* Get optional forth parameter. It must be a constant. */
/* Get optional fourth parameter. It must be a constant. */
stop_item = vpi_scan(argv);
if (stop_item!=0){
if (check_integer_constant(name, stop_item) == 0){
@ -188,7 +188,7 @@ static PLI_INT32 sys_readmem_calltf(char*name)
return 0;
}
/* Check that ther is no 5th parameter */
/* Check that there is no 5th parameter */
if (vpi_scan(argv) != 0){
vpi_printf("ERROR: %s accepts maximum 4 parameters!\n", name );
vpi_free_object(argv);
@ -424,7 +424,7 @@ static PLI_INT32 sys_writemem_calltf(char*name)
return 0;
}
/* Get optional forth parameter. It must be a constant. */
/* Get optional fourth parameter. It must be a constant. */
stop_item = vpi_scan(argv);
if (stop_item!=0){
if (check_integer_constant(name, stop_item) == 0){
@ -432,7 +432,7 @@ static PLI_INT32 sys_writemem_calltf(char*name)
return 0;
}
/* Check that ther is no 5th parameter */
/* Check that there is no 5th parameter */
if (vpi_scan(argv) != 0){
vpi_printf("ERROR: %s accepts maximum 4 parameters!\n", name );
vpi_free_object(argv);
@ -450,7 +450,7 @@ static PLI_INT32 sys_writemem_calltf(char*name)
/* Open the data file. */
file = fopen(path, "w");
if (file == 0) {
vpi_printf("%s: Unable to open %s for writeing.\n", name, path);
vpi_printf("%s: Unable to open %s for writing.\n", name, path);
free(path);
return 0;
}

2
vpi/sys_vcd.c
View File

@ -21,7 +21,7 @@
/*
* This file contains the implementations of the VCD related
* funcitons.
* functions.
*/
# include "vpi_user.h"

2
vpi/vcd_priv.c
View File

@ -109,7 +109,7 @@ void vcd_names_sort(struct vcd_names_list_s*tab)
The new signal will be listed as a $var, but no callback
will be installed. This saves considerable CPU time and leads
to smalle VCD files.
to smaller VCD files.
The _vpiNexusId is a private (int) property of IVL simulators.
*/

2
vpip/vpi_bit.c
View File

@ -107,7 +107,7 @@ vpip_bit_t vpip_pair_resolve(vpip_bit_t a, vpip_bit_t b)
res = tmp;
}
/* Cannonicalize the HiZ value. */
/* Canonicalize the HiZ value. */
if ((res&0x77) == 0)
res = HiZ;

2
vpip/vpi_callback.c
View File

@ -83,7 +83,7 @@ void vpip_run_value_changes(struct __vpiSignal*sig)
/*
* Handle read-only synch events. This causes the callback to be
* scheduled for a moment at the end of the time period. This method
* handles scheduling with itme delays.
* handles scheduling with time delays.
*/
static void go_readonly_synch(struct __vpiCallback*rfp)
{

4
vpip/vpi_priv.h
View File

@ -224,7 +224,7 @@ extern struct __vpiNull *vpip_get_null(void);
* This type represents the handle to a Verilog scope. These include
* module instantiations and name begin-end blocks. The attach
* function is used to attach handles to the scope by the runtime
* initializaiton.
* initialization.
*/
struct __vpiScope {
struct __vpiHandle base;
@ -380,7 +380,7 @@ extern void vpip_simulation_run();
extern void vpi_mcd_init(void);
/*
* Schedule an event to be run sometime in the future. The d parmater
* Schedule an event to be run sometime in the future. The d parameter
* is the delay in simulation units before the event is processed. If
* the non-block flag is set, the event is scheduled to happen at the
* end of the time step.

2
vpip/vpi_time.c
View File

@ -25,7 +25,7 @@
# include <stdio.h>
/*
* IEEE-1364 VPI pretty much mandates the existance of this sort of
* IEEE-1364 VPI pretty much mandates the existence of this sort of
* thing. (Either this or a huge memory leak.) Sorry.
*/
static char buf_obj[128];

12
vvp/README.txt
View File

@ -29,7 +29,7 @@ semicolon that terminates a statement. Like so:
The semicolon is required, whether the comment is there or not.
Statements may span multiple lines, as long as there is no text (other
then the first character of a label) in the first column of the
than the first character of a label) in the first column of the
continuation line.
HEADER SYNTAX
@ -83,7 +83,7 @@ references symbolically.)
If the functor is part of a vector, then the symbol is the
vvp_ipoint_t for the first functor. The [] operator can then be used
to reference a functor other then the first in the vector.
to reference a functor other than the first in the vector.
There are some special symbols that in certain contexts have special
meanings. As inputs to functors, the symbols "C<0>", "C<1>", "C<x>"
@ -139,7 +139,7 @@ implementation. Most of the core gate types have built in tables.
The initial values of all the inputs and the output is x. Any other
value is passed around as run-time behavior. If the inputs have C<?>
symbols, then the inputs are initialized to the specified bit value,
and if this causes the output to be something other then x, a
and if this causes the output to be something other than x, a
propagation event is created to be executed at the start of run time.
The strengths of inputs are ignored by functors, and the output has
@ -234,7 +234,7 @@ sake of VPI code that might access it. The variable is placed in the
current scope. The variable also has a width, defined by the indices
for the most significant and lest significant bits. If the indices are
equal (normally 0) the vector has width of one. If the width is greater
then one, a contiguous array of functors is created and the value of
than one, a contiguous array of functors is created and the value of
the label is the address of the least significant bit.
A variable does not take inputs, since its value is set behaviorally
@ -619,7 +619,7 @@ of four possible values (0, 1, x and z) so two bits are needed to
represent them. So the input of the functor is 8 bits, and the output
2 bits. A complete lookup table for generating the 2-bit output from
an 8-bit input is 512 bits. That can be packed into 64 bytes. This is
small enough that the table should take less space then the code to
small enough that the table should take less space than the code to
implement the logic.
To implement the truth table, we need to assign 2-bit encodings for
@ -779,7 +779,7 @@ becomes:
Notice the first parameter of the .functor is the type. The type
includes a truth table that describes the output with a given
input. If the gate is wider then four inputs, then cascade
input. If the gate is wider than four inputs, then cascade
functors. For example:
and gate (out, i1, i2, i3, i4, i5, i6, i7, i8);

2
vvp/compile.cc
View File

@ -669,7 +669,7 @@ void inputs_connect(vvp_ipoint_t fdx, unsigned argc, struct symb_s*argv)
for (unsigned idx = 0; idx < argc; idx += 1) {
/* Find the functor for this input. This assumes that
wide (more then 4 inputs) gates are consecutive
wide (more than 4 inputs) gates are consecutive
functors. */
vvp_ipoint_t ifdx = ipoint_input_index(fdx, idx);
functor_t iobj = functor_index(ifdx);

2
vvp/examples/memory.vvp
View File

@ -59,7 +59,7 @@ m .var "m", 6,0;
;;; memory words occupy 8 bits each, that is 7 rounded up to the next
;;; multiple of 4.
;;; Four bits ber byte. Word fill bits are included. Commas are
;;; Four bits per byte. Word fill bits are included. Commas are
;;; optional, there may be a comma after the last byte.
.mem/init memory[20],

12
vvp/opcodes.txt
View File

@ -9,7 +9,7 @@
EXECUTABLE INSTRUCTION OPCODES
Instruction opcodes all start with a % character and have 0 or more
operands. In no case are there more then 3 operands. This chapter
operands. In no case are there more than 3 operands. This chapter
describes the specific behavior of each opcode, in enough detail
(I hope) that its complete effect can be predicted.
@ -160,8 +160,8 @@ same, or 0 otherwise. The eq bit is true if the values are logically
the same. That is, x and z are considered equal. In other words the eq
bit is the same as ``=='' and the eeq bit ``===''.
The lt bit is 1 if the left vector is less then the right vector, or 0
if greater then or equal to the right vector. It is the equivalent of
The lt bit is 1 if the left vector is less than the right vector, or 0
if greater than or equal to the right vector. It is the equivalent of
the Verilog < operator. Combinations of these three bits can be used
to implement all the Verilog comparison operators.
@ -252,7 +252,7 @@ thread to start executing at the specified address. The new thread is
created and pushed onto the child stack. It is also marked runnable,
but is not necessarily started until the current thread yields.
The %fork instruction has no effect other then to push a child thread.
The %fork instruction has no effect other than to push a child thread.
See also %join.
@ -327,7 +327,7 @@ will jump to T_label if bit 8 is x or z.
This is the partner to %fork. This instruction causes the thread to
wait for the top thread in the child stack to terminate, then
continues. It has no effect in the current thread other then to wait
continues. It has no effect in the current thread other than to wait
until the top child is cleared.
It is an error to execute %join if there are no children in the child
@ -539,7 +539,7 @@ complete bounds checking.
The %set/x0/x instruction is the same, except the bound value is in
a word register instead of in the opcode. This allows for bounds that
are larger then 0xffff.
are larger than 0xffff.
* %shiftl/i0 <bit>, <wid>

2
vvp/udp.h
View File

@ -53,7 +53,7 @@ struct vvp_udp_s *udp_find(char *label);
* also points to the vvp_udp_s table that is the behavior for the
* device.
*
* If there are more then 4 inputs to the device, then enough
* If there are more than 4 inputs to the device, then enough
* edge_inputs_functor_s functors is created to receive all the
* inputs. All the edge_inputs_functors_s ::out members point to the
* leading udp_functor_s object, so the ::set methods all invoke the

4
vvp/vpi.txt
View File

@ -11,7 +11,7 @@ System tasks and functions in Verilog are implemented in Icarus
Verilog by C routines written with VPI. This implies that the vvp
engine must provide at least a subset of the Verilog VPI
interface. The minimalist concepts of vvp, however, make the method
less then obvious.
less than obvious.
Within a Verilog design, there is a more or less fixed web of
vpiHandles that is the design database as is available to VPI
@ -108,7 +108,7 @@ A scope is created with a .scope directive, like so:
The scope takes a string name as the first parameter. If there is an
additional parameter, it is a label of the directive for the parent
scope. Scopes that have no parent are root scopes. It is an error to
declare a scope with the same name more then once in a parent scope.
declare a scope with the same name more than once in a parent scope.
The name string given when creating the scope is the basename for the
scope. The vvp automatically constructs full names from the scope

2
vvp/vpi_mcd.cc
View File

@ -227,7 +227,7 @@ extern "C" FILE *vpi_get_file(PLI_INT32 fd)
// Only deal with FD's
if (IS_MCD(fd)) return NULL;
// Only know about FD_MAX indicies
// Only know about FD_MAX indices
if (FD_IDX(fd) >= FD_MAX) return NULL;
return fd_table[FD_IDX(fd)].fp;

2
vvp/vpi_modules.cc
View File

@ -75,7 +75,7 @@ void vpip_load_module(const char*name)
sprintf(buf, "%s.vpi", name);
rc = stat(buf, &sb);
/* Tray alwo with the .vpl suffix. */
/* Try also with the .vpl suffix. */
if (rc != 0) {
export_flag = true;
sprintf(buf, "%s.vpl", name);

2
vvp/vpi_tasks.cc
View File

@ -281,7 +281,7 @@ static const struct __vpirt vpip_sysfunc_real_rt = {
systask_iter
};
/* **** Manipulate the internal datastructures. **** */
/* **** Manipulate the internal data structures. **** */
static struct __vpiUserSystf**def_table = 0;
static unsigned def_count = 0;

4
vvp/vthread.cc
View File

@ -345,7 +345,7 @@ void vthread_run(vthread_t thr)
}
/*
* The CHUNK_LINK instruction is a specla next pointer for linking
* The CHUNK_LINK instruction is a special next pointer for linking
* chunks of code space. It's like a simplified %jmp.
*/
bool of_CHUNK_LINK(vthread_t thr, vvp_code_t code)
@ -2862,7 +2862,7 @@ bool of_FORK_UFUNC(vthread_t thr, vvp_code_t cp)
/* After this function, the .ufunc code has placed an of_JOIN
to pause this thread. Since the child was pushed by the
flag to schecule_vthread, the called function starts up
flag to schedule_vthread, the called function starts up
immediately. */
return true;
}

2
xnfio.cc
View File

@ -305,7 +305,7 @@ void xnfio_f::lpm_compare(Design*des, NetCompare*dev)
bool xnfio_f::compare_sideb_const(Design*des, NetCompare*dev)
{
/* Even if side B is all constant, if there are more then 4
/* Even if side B is all constant, if there are more than 4
signals on side A we will not be able to fit the operation
into a function unit, so we might as well accept a
comparator. Give up. */