luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'master' of steve-icarus@icarus.com:git/verilog

This commit is contained in:
Stephen Williams 2008-01-28 21:33:14 -08:00
parent 685095b229 388bb93beb
commit 76039cf595
22 changed files with 40 additions and 320 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
BUGS.txt
View File

@ -72,7 +72,7 @@ reporting problems with. However, if you clearly explain what is right
and wrong about the generated netlist, I will probably be able to fix and wrong about the generated netlist, I will probably be able to fix
the problem. It may take a few iterations. the problem. It may take a few iterations.
In this case, if possible include not only the sample verilog program, In this case, if possible include not only the sample Verilog program,
but the generated netlist file(s) and a clear indication of what went but the generated netlist file(s) and a clear indication of what went
wrong. If it is not clear to me, I will ask for clarification. wrong. If it is not clear to me, I will ask for clarification.

4
Makefile.in
View File

@ -41,8 +41,6 @@ libdir = @libdir@
includedir = @includedir@ includedir = @includedir@
mandir = @mandir@ mandir = @mandir@
libdir64 = @libdir64@
dllib=@DLLIB@ dllib=@DLLIB@
CC = @CC@ CC = @CC@
@ -147,8 +145,6 @@ iverilog-vpi: iverilog-vpi.sh
-e 's;@IVCXX@;$(CXX);' \ -e 's;@IVCXX@;$(CXX);' \
-e 's;@IVCFLAGS@;$(CXXFLAGS);' \ -e 's;@IVCFLAGS@;$(CXXFLAGS);' \
-e 's;@INCLUDEDIR@;@includedir@;' \ -e 's;@INCLUDEDIR@;@includedir@;' \
-e 's;@LIBDIR64@;@libdir64@;' \
-e 's;@VPIDIR1@;@vpidir1@;' -e 's;@VPIDIR2@;@vpidir2@;' \
-e 's;@LIBDIR@;@libdir@;' $< > $@ -e 's;@LIBDIR@;@libdir@;' $< > $@
chmod +x $@ chmod +x $@
endif endif

14
cadpli/Makefile.in
View File

@ -33,7 +33,7 @@ bindir = @bindir@
libdir = @libdir@ libdir = @libdir@
includedir = $(prefix)/include includedir = $(prefix)/include
vpidir = @libdir@/ivl/@vpidir1@ vpidir = @libdir@/ivl
CC = @CC@ CC = @CC@
INSTALL = @INSTALL@ INSTALL = @INSTALL@
@ -48,14 +48,6 @@ SHARED = @shared@
all: all:
ifeq (@enable_vvp32@,yes)
vpidir32 = $(libdir)/ivl/@vpidir2@
ALL32 = all32
INSTALL32 = install32
UNINSTALL32 = uninstall32
include $(srcdir)/enable_vvp32.mk
endif
all: dep cadpli.vpl $(ALL32) all: dep cadpli.vpl $(ALL32)
# No specific check operations. # No specific check operations.
@ -97,8 +89,4 @@ uninstall: $(UNINSTALL32)
uninstall32: uninstall32:
ifeq (@enable_vvp32@,yes)
include $(srcdir)/enable_vvp32.mk
endif
-include $(patsubst %.o, dep/%.d, $O) -include $(patsubst %.o, dep/%.d, $O)

15
cadpli/configure.in
View File

@ -12,10 +12,6 @@ AX_WIN32
AC_PROG_INSTALL AC_PROG_INSTALL
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_CHECK_HEADERS(malloc.h) AC_CHECK_HEADERS(malloc.h)
AC_CHECK_SIZEOF(unsigned long long) AC_CHECK_SIZEOF(unsigned long long)
@ -62,15 +58,4 @@ AX_C_UNDERSCORES_TRAILING
AX_CPP_IDENT AX_CPP_IDENT
# where to put vpi subdirectories
AC_MSG_CHECKING(for VPI subdirectories)
if test x${vpidir1} = x
then
vpidir1="."
fi
AC_SUBST(vpidir1)
AC_SUBST(vpidir2)
AC_MSG_RESULT(${vpidir1} ${vpidir2})
AC_OUTPUT(Makefile) AC_OUTPUT(Makefile)

39
cadpli/enable_vvp32.mk
View File

@ -1,39 +0,0 @@
#
# This source code is free software; you can redistribute it
# and/or modify it in source code form under the terms of the GNU
# Library General Public License as published by the Free Software
# Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Library General Public License for more details.
#
# You should have received a copy of the GNU Library General Public
# License along with this program; if not, write to the Free
# Software Foundation, Inc.,
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
#ident "$Id: enable_vvp32.mk,v 1.1 2003/10/09 01:07:20 steve Exp $"
#
all32: bin32 bin32/cadpli.vpl
bin32:
mkdir bin32
bin32/%.o: %.c
$(CC) -m32 -Wall -I$(srcdir) -I$(srcdir)/.. $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $@
bin32/cadpli.vpl: $(addprefix bin32/,$O) ../vvp/bin32/libvpi.a ../libveriuser/bin32/libveriuser.o
$(CC) $(SHARED) -m32 -o $@ $(addprefix bin32/,$O) ../libveriuser/bin32/libveriuser.o ../vvp/bin32/libvpi.a
install32: all32 $(vpidir32)/cadpli.vpl
$(vpidir32)/cadpli.vpl: bin32/cadpli.vpl
$(INSTALL_PROGRAM) bin32/cadpli.vpl $(vpidir32)/cadpli.vpl
uninstall32:
rm -f $(vpidir32)/cadpli.vpl

26
configure.in
View File

@ -42,11 +42,6 @@ AC_SUBST(EXEEXT)
# Combined check for Microsoft-related bogosities; sets WIN32 if found # Combined check for Microsoft-related bogosities; sets WIN32 if found
AX_WIN32 AX_WIN32
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_LANG_CPLUSPLUS AC_LANG_CPLUSPLUS
AC_CHECK_HEADERS(getopt.h malloc.h inttypes.h libiberty.h iosfwd sys/wait.h) AC_CHECK_HEADERS(getopt.h malloc.h inttypes.h libiberty.h iosfwd sys/wait.h)
@ -123,27 +118,6 @@ AX_C_UNDERSCORES_TRAILING
AX_CPP_IDENT AX_CPP_IDENT
# If not otherwise specified, set the libdir64 variable
# to the same as libdir.
AC_MSG_CHECKING(for libdir64 path)
if test x${libdir64} = x
then
libdir64="${libdir}"
fi
AC_SUBST(libdir64)
AC_MSG_RESULT(${libdir64})
# where to put vpi subdirectories
AC_MSG_CHECKING(for VPI subdirectories)
if test x${vpidir1} = x
then
vpidir1="."
fi
AC_SUBST(vpidir1)
AC_SUBST(vpidir2)
AC_MSG_RESULT(${vpidir1} ${vpidir2})
# XXX disable tgt-fpga for the moment # XXX disable tgt-fpga for the moment
AC_CONFIG_SUBDIRS(vvp vpi tgt-stub tgt-null tgt-vvp libveriuser cadpli) AC_CONFIG_SUBDIRS(vvp vpi tgt-stub tgt-null tgt-vvp libveriuser cadpli)

6
examples/pal_reg.v
View File

@ -26,7 +26,7 @@
* iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v * iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v
* *
* The output file name (passed through the -o<file> switch) can be * The output file name (passed through the -o<file> switch) can be
* any file you desire. If the compilation and fittin all succeed, the * any file you desire. If the compilation and fitting all succeed, the
* output file will be a JEDEC file that you can take to your favorite * output file will be a JEDEC file that you can take to your favorite
* PROM programmer to program the part. * PROM programmer to program the part.
* *
@ -45,7 +45,7 @@
* *
* The output drivers are controlled by a single active low output * The output drivers are controlled by a single active low output
* enable. I used bufif0 devices in this example, but the exact same * enable. I used bufif0 devices in this example, but the exact same
* thing can be achived with a continuous assignment like so: * thing can be achieved with a continuous assignment like so:
* *
* assign out = oe? 8'hzz : Q; * assign out = oe? 8'hzz : Q;
* *
@ -76,7 +76,7 @@ endmodule
* a PLCC package. * a PLCC package.
* *
* Note that this module has no logic in it. It is a convention I use * Note that this module has no logic in it. It is a convention I use
* that I put all the functionality in a seperate module (seen above) * that I put all the functionality in a separate module (seen above)
* and isolate the Icarus Verilog specific $attribute madness into a * and isolate the Icarus Verilog specific $attribute madness into a
* top-level module. The advantage of this style is that the entire * top-level module. The advantage of this style is that the entire
* module can be `ifdef'ed out when doing simulation and you don't * module can be `ifdef'ed out when doing simulation and you don't

2
examples/show_vcd.vl
View File

@ -63,7 +63,7 @@
* *
* The $dumpvars task tells the simulation what variables to write to * The $dumpvars task tells the simulation what variables to write to
* the VCD output. The first parameter is how far to descend while * the VCD output. The first parameter is how far to descend while
* scanning a scope, and the remaining paramters are signals or scope * scanning a scope, and the remaining parameters are signals or scope
* names to include in the dump. If a scope name is given, all the * names to include in the dump. If a scope name is given, all the
* signals within the scope are dumped. If a wire or register name is * signals within the scope are dumped. If a wire or register name is
* given, that signal is included. * given, that signal is included.

8
examples/sqrt-virtex.v
View File

@ -20,7 +20,7 @@
*/ */
/* /*
* This module is a synthesizeable square-root function. It is also a * This module is a synthesizable square-root function. It is also a
* detailed example of how to target Xilinx Virtex parts using * detailed example of how to target Xilinx Virtex parts using
* Icarus Verilog. In fact, for no particular reason other than to * Icarus Verilog. In fact, for no particular reason other than to
* be excessively specific, I will step through the process of * be excessively specific, I will step through the process of
@ -30,7 +30,7 @@
* In addition to Icarus Verilog, you will need implementation * In addition to Icarus Verilog, you will need implementation
* software from Xilinx. As of this writing, this example was tested * software from Xilinx. As of this writing, this example was tested
* with Foundation 4.2i, but it should work the same with ISE and * with Foundation 4.2i, but it should work the same with ISE and
* Webpack software. * WebPACK software.
* *
* This example source contains all the Verilog needed to do * This example source contains all the Verilog needed to do
* everything described below. We use conditional compilation to * everything described below. We use conditional compilation to
@ -55,7 +55,7 @@
* "PASSED" and finishes the simulation. * "PASSED" and finishes the simulation.
* *
* When you take a close look at the "main" module below, you will see * When you take a close look at the "main" module below, you will see
* that it uses Verilog constructs that are not synthesizeable. This * that it uses Verilog constructs that are not synthesizable. This
* is fine, as we will never try to synthesize it. * is fine, as we will never try to synthesize it.
* *
* LIBRARY PARTS * LIBRARY PARTS
@ -78,7 +78,7 @@
* Without any preprocessor directives, the only module is the sqrt32 * Without any preprocessor directives, the only module is the sqrt32
* module, so sqrt32 is compiled as the root. The ports of the module * module, so sqrt32 is compiled as the root. The ports of the module
* are automatically made into ports of the sqrt32.edf netlist, and * are automatically made into ports of the sqrt32.edf netlist, and
* the contents of the sqrt32 module are connected approprately. * the contents of the sqrt32 module are connected appropriately.
* *
* COMPLETE CHIP DESIGNS * COMPLETE CHIP DESIGNS
* *

20
iverilog-vpi.sh
View File

@ -26,20 +26,9 @@ CFLAGS="@PIC@ @IVCFLAGS@ -I@INCLUDEDIR@"
# These are used for linking... # These are used for linking...
LD=$CC LD=$CC
LDFLAGS32="@SHARED@ -L@LIBDIR@" LDFLAGS="@SHARED@ -L@LIBDIR@"
LDFLAGS64="@SHARED@ -L@LIBDIR64@"
LDFLAGS="$LDFLAGS64"
LDLIBS="-lveriuser -lvpi" LDLIBS="-lveriuser -lvpi"
INSTDIR64="@VPIDIR1@"
INSTDIR32="@VPIDIR2@"
if test x$INSTDIR32 = x
then
INSTDIR32=$INSTDIR64
fi
INSTDIR="$INSTDIR64"
CCSRC= CCSRC=
CXSRC= CXSRC=
OBJ= OBJ=
@ -96,11 +85,6 @@ do
-D*) DEFS="$DEFS $parm" -D*) DEFS="$DEFS $parm"
;; ;;
-m32) LDFLAGS="-m32 $LDFLAGS32"
CFLAGS="-m32 $CFLAGS"
INSTDIR="$INSTDIR32"
;;
--cflags) --cflags)
echo "$CFLAGS" echo "$CFLAGS"
exit; exit;
@ -117,7 +101,7 @@ do
;; ;;
--install-dir) --install-dir)
echo "@LIBDIR@/ivl/$INSTDIR" echo "@LIBDIR@/ivl"
exit exit
;; ;;
esac esac

42
libveriuser/Makefile.in
View File

@ -30,7 +30,6 @@ VPATH = $(srcdir)
bindir = @bindir@ bindir = @bindir@
libdir = @libdir@ libdir = @libdir@
libdir64 = @libdir64@
includedir = $(prefix)/include includedir = $(prefix)/include
CC = @CC@ CC = @CC@
@ -58,12 +57,6 @@ getlongp.o getp.o getsimtime.o io_print.o math.o mc_scan_plusargs.o \
nodeinfo.o nump.o putlongp.o putp.o spname.o typep.o workarea.o \ nodeinfo.o nump.o putlongp.o putp.o spname.o typep.o workarea.o \
veriusertfs.o priv.o $A veriusertfs.o priv.o $A
ifeq (@enable_vvp32@,yes)
ALL32 = all32
INSTALL32 = install32
UNINSTALL32 = uninstall32
endif
all: dep libveriuser.a $(ALL32) all: dep libveriuser.a $(ALL32)
check: all check: all
@ -93,40 +86,15 @@ clean:
distclean: clean distclean: clean
rm -f Makefile config.status config.log config.cache config.h rm -f Makefile config.status config.log config.cache config.h
install:: all installdirs $(libdir64)/libveriuser.a $(INSTALL32) install:: all installdirs $(libdir)/libveriuser.a $(INSTALL32)
$(libdir64)/libveriuser.a: ./libveriuser.a $(libdir)/libveriuser.a: ./libveriuser.a
$(INSTALL_DATA) ./libveriuser.a $(libdir64)/libveriuser.a $(INSTALL_DATA) ./libveriuser.a $(libdir)/libveriuser.a
installdirs: mkinstalldirs installdirs: mkinstalldirs
$(srcdir)/mkinstalldirs $(includedir) $(libdir64) $(srcdir)/mkinstalldirs $(includedir) $(libdir)
uninstall:: uninstall::
rm -f $(libdir64)/libveriuser.a rm -f $(libdir)/libveriuser.a
ifeq (@enable_vvp32@,yes)
all32: bin32 bin32/libveriuser.a
bin32:
mkdir bin32
bin32/%.o: %.c
$(CC) -m32 $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $@
bin32/libveriuser.o: $(addprefix bin32/,$O)
$(LD) -melf_i386 -r -o $@ $(addprefix bin32/,$O)
bin32/libveriuser.a: bin32/libveriuser.o
rm -f $@
ar cvq $@ bin32/libveriuser.o
$(RANLIB) $@
install32: $(libdir)/libveriuser.a
$(libdir)/libveriuser.a: bin32/libveriuser.a
$(INSTALL_DATA) bin32/libveriuser.a $(libdir)/libveriuser.a
-include $(patsubst bin32/%.o, bin32/%.d, $(addprefix bin32/,$O))
endif
-include $(patsubst %.o, dep/%.d, $O) -include $(patsubst %.o, dep/%.d, $O)

14
libveriuser/configure.in
View File

@ -10,10 +10,6 @@ AC_PROG_RANLIB
AC_EXEEXT AC_EXEEXT
AX_CPP_IDENT AX_CPP_IDENT
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_CHECK_HEADERS(malloc.h) AC_CHECK_HEADERS(malloc.h)
AC_CHECK_SIZEOF(unsigned long long) AC_CHECK_SIZEOF(unsigned long long)
@ -29,14 +25,4 @@ AX_C_PICFLAG
AC_SUBST(EXEEXT) AC_SUBST(EXEEXT)
AC_SUBST(EXTRALIBS) AC_SUBST(EXTRALIBS)
# If not otherwise specified, set the libdir64 variable
# to the same as libdir.
AC_MSG_CHECKING(for libdir64 path)
if test x${libdir64} = x
then
libdir64="${libdir}"
fi
AC_SUBST(libdir64)
AC_MSG_RESULT(${libdir64})
AC_OUTPUT(Makefile) AC_OUTPUT(Makefile)

4
mingw.txt
View File

@ -91,7 +91,7 @@ commands below.
The obvious step 2, then, is install the mingw compilers. These can be The obvious step 2, then, is install the mingw compilers. These can be
found at the web page <http://www.mingw.org>. The Mingw-5.x.x package found at the web page <http://www.mingw.org>. The Mingw-5.x.x package
is a convenient remote installer. Download this program and run is a convenient remote installer. Download this program and run
it. The installer will ask wich components you want to install. You it. The installer will ask which components you want to install. You
need only the base C compiler and the C++ compiler. (You may install need only the base C compiler and the C++ compiler. (You may install
other languages if you wish.) other languages if you wish.)
@ -150,7 +150,7 @@ You will need these gnuwin32 packages to compile Icarus Verilog:
I suggest creating a common directory for holding all your gnuwin32 I suggest creating a common directory for holding all your gnuwin32
packages. I use C:\gnuwin32. The download page at the gnuwin32 site packages. I use C:\gnuwin32. The download page at the gnuwin32 site
has a "setup" link for each of these packages. Click the setup to has a "setup" link for each of these packages. Click the setup to
download the installer for each of the desired programes, then execute download the installer for each of the desired programs, then execute
the downloaded .exe files to invoke the installer. Install into the the downloaded .exe files to invoke the installer. Install into the
c:\gunwin32 directory. c:\gunwin32 directory.

2
net_nex_output.cc
View File

@ -105,7 +105,7 @@ void NetPDelay::nex_output(NexusSet&out)
/* /*
* For the purposes of synthesis, system task calls have no output at * For the purposes of synthesis, system task calls have no output at
* all. This is OK because most system tasks are not synthesizeable in * all. This is OK because most system tasks are not synthesizable in
* the first place. * the first place.
*/ */
void NetSTask::nex_output(NexusSet&out) void NetSTask::nex_output(NexusSet&out)

24
verilog.spec
View File

@ -12,16 +12,6 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-20070812-%{release}-root
BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, readline-devel BuildRequires: gcc-c++, zlib-devel, bison, flex, gperf, readline-devel
%ifarch x86_64
BuildRequires: bzip2-32bit, glibc-devel-32bit, glibc-32bit, zlib-devel-32bit
BuildRequires: termcap-32bit, readline-32bit, readline-devel-32bit
%if 0%{?suse_version} == 1020
BuildRequires: gcc-32bit, libstdc++41-devel-32bit
%endif
%endif
# This provides tag allows me to use a more specific name for things # This provides tag allows me to use a more specific name for things
# that actually depend on me, Icarus Verilog. # that actually depend on me, Icarus Verilog.
Provides: iverilog Provides: iverilog
@ -35,11 +25,7 @@ to the IEEE-1364 standard.
%setup -n verilog-20070812 %setup -n verilog-20070812
%build %build
%ifarch x86_64
./configure --prefix=/usr --mandir='$(prefix)/share/man' libdir64='$(prefix)/lib64' vpidir1=vpi64 vpidir2=. --enable-vvp32
%else
./configure --prefix=/usr --mandir='$(prefix)/share/man' ./configure --prefix=/usr --mandir='$(prefix)/share/man'
%endif
make CXXFLAGS=-O make CXXFLAGS=-O
%install %install
@ -77,13 +63,6 @@ rm -rf $RPM_BUILD_ROOT
#%attr(-,root,root) /usr/lib/ivl/fpga-s.conf #%attr(-,root,root) /usr/lib/ivl/fpga-s.conf
#%attr(-,root,root) /usr/lib/ivl/xnf.conf #%attr(-,root,root) /usr/lib/ivl/xnf.conf
#%attr(-,root,root) /usr/lib/ivl/xnf-s.conf #%attr(-,root,root) /usr/lib/ivl/xnf-s.conf
%ifarch x86_64
%attr(-,root,root) /usr/bin/vvp32
%attr(-,root,root) /usr/lib/ivl/vpi64/system.vpi
%attr(-,root,root) /usr/lib/ivl/vpi64/cadpli.vpl
%attr(-,root,root) /usr/lib64/libvpi.a
%attr(-,root,root) /usr/lib64/libveriuser.a
%endif
%attr(-,root,root) /usr/lib/ivl/system.sft %attr(-,root,root) /usr/lib/ivl/system.sft
%attr(-,root,root) /usr/lib/ivl/system.vpi %attr(-,root,root) /usr/lib/ivl/system.vpi
%attr(-,root,root) /usr/lib/ivl/cadpli.vpl %attr(-,root,root) /usr/lib/ivl/cadpli.vpl
@ -98,3 +77,6 @@ rm -rf $RPM_BUILD_ROOT
%changelog -n verilog %changelog -n verilog
* Sun Feb 28 2007 - steve@icarus.com * Sun Feb 28 2007 - steve@icarus.com
- Added formatting suitable for openSUSE packaging. - Added formatting suitable for openSUSE packaging.
* Fri Jan 25 2008 - steve@icarus.com
- Removed vvp32 support for x86_64 build.

2
verinum.cc
View File

@ -290,7 +290,7 @@ uint64_t verinum::as_ulong64() const
* *
* If the value is undefined, return 0. * If the value is undefined, return 0.
* *
* This function presumes that the native format is 2s compliment * This function presumes that the native format is 2s complement
* (pretty safe these days) and masks/sets bits accordingly. If the * (pretty safe these days) and masks/sets bits accordingly. If the
* value is too large for the native form, it truncates the high bits. * value is too large for the native form, it truncates the high bits.
*/ */

35
vpi/Makefile.in
View File

@ -33,7 +33,7 @@ bindir = @bindir@
libdir = @libdir@ libdir = @libdir@
includedir = $(prefix)/include includedir = $(prefix)/include
vpidir = $(libdir)/ivl/@vpidir1@ vpidir = $(libdir)/ivl
CC = @CC@ CC = @CC@
INSTALL = @INSTALL@ INSTALL = @INSTALL@
@ -46,13 +46,6 @@ CPPFLAGS = @ident_support@ -I. -I$(srcdir)/.. -I$(srcdir) -I.. @file64_support@
CFLAGS = -Wall @CFLAGS@ CFLAGS = -Wall @CFLAGS@
LDFLAGS = @LDFLAGS@ LDFLAGS = @LDFLAGS@
ifeq (@enable_vvp32@,yes)
vpidir32 = $(libdir)/ivl/@vpidir2@
ALL32 = all32
INSTALL32 = install32
UNINSTALL32 = uninistall32
endif
all: dep system.vpi $(ALL32) all: dep system.vpi $(ALL32)
dep: dep:
@ -95,28 +88,6 @@ sdf_lexor.c: sdf_lexor.lex
sdf_parse.c sdf_parse.h: $(srcdir)/sdf_parse.y sdf_parse.c sdf_parse.h: $(srcdir)/sdf_parse.y
$(YACC) --verbose -d -p sdf -o sdf_parse.c $(srcdir)/sdf_parse.y $(YACC) --verbose -d -p sdf -o sdf_parse.c $(srcdir)/sdf_parse.y
ifeq (@enable_vvp32@,yes)
all32: bin32 bin32/system.vpi
bin32:
mkdir bin32
bin32/%.o: %.c
$(CC) -m32 $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $@
bin32/system.vpi: $(addprefix bin32/,$O)
$(CC) -m32 @shared@ -o $@ $(addprefix bin32/,$O) -L../vvp/bin32 $(LDFLAGS) -lvpi $(SYSTEM_VPI_LDFLAGS)
install32: all32 $(vpidir32)/system.vpi
$(vpidir32)/system.vpi: bin32/system.vpi
$(INSTALL_PROGRAM) bin32/system.vpi $(vpidir32)/system.vpi
uninstall32:
rm -f $(vpidir32)/system.vpi
endif
clean: clean:
rm -rf *.o sys_readmem_lex.c dep system.vpi bin32 rm -rf *.o sys_readmem_lex.c dep system.vpi bin32
rm -f sdf_lexor.c sdf_parse.c sdf_parse.output sdf_parse.h rm -f sdf_lexor.c sdf_parse.c sdf_parse.output sdf_parse.h
@ -126,7 +97,7 @@ distclean: clean
check: all check: all
install: all installdirs $(vpidir)/system.vpi $(libdir)/ivl/system.sft $(INSTALL32) install: all installdirs $(vpidir)/system.vpi $(libdir)/ivl/system.sft
$(vpidir)/system.vpi: ./system.vpi $(vpidir)/system.vpi: ./system.vpi
$(INSTALL_PROGRAM) ./system.vpi $(vpidir)/system.vpi $(INSTALL_PROGRAM) ./system.vpi $(vpidir)/system.vpi
@ -137,7 +108,7 @@ $(libdir)/ivl/system.sft: system.sft
installdirs: ../mkinstalldirs installdirs: ../mkinstalldirs
$(srcdir)/../mkinstalldirs $(vpidir) $(srcdir)/../mkinstalldirs $(vpidir)
uninstall: $(UNINSTALL32) uninstall:
rm -f $(vpidir)/system.vpi rm -f $(vpidir)/system.vpi
rm -f $(libdir)/ivl/system.sft rm -f $(libdir)/ivl/system.sft

26
vpi/configure.in
View File

@ -31,11 +31,6 @@ AX_WIN32
AX_CPP_IDENT AX_CPP_IDENT
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_CHECK_HEADERS(malloc.h inttypes.h) AC_CHECK_HEADERS(malloc.h inttypes.h)
AC_CHECK_LIB(z, gzwrite) AC_CHECK_LIB(z, gzwrite)
@ -99,25 +94,4 @@ AX_LD_SHAREDLIB_OPTS
AX_CPP_IDENT AX_CPP_IDENT
# If not otherwise specified, set the libdir64 variable
# to the same as libdir.
AC_MSG_CHECKING(for libdir64 path)
if test x${libdir64} = x
then
libdir64="${libdir}"
fi
AC_SUBST(libdir64)
AC_MSG_RESULT(${libdir64})
# where to put vpi subdirectories
AC_MSG_CHECKING(for VPI subdirectories)
if test x${vpidir1} = x
then
vpidir1="."
fi
AC_SUBST(vpidir1)
AC_SUBST(vpidir2)
AC_MSG_RESULT(${vpidir1} ${vpidir2})
AC_OUTPUT(Makefile) AC_OUTPUT(Makefile)

61
vvp/Makefile.in
View File

@ -33,8 +33,6 @@ libdir = @libdir@
mandir = @mandir@ mandir = @mandir@
includedir = @includedir@ includedir = @includedir@
libdir64 = @libdir64@
CC = @CC@ CC = @CC@
HOSTCC = @CC@ HOSTCC = @CC@
CXX = @CXX@ CXX = @CXX@
@ -58,13 +56,7 @@ ifneq (x@vpidir2@,x)
MDIR2 = -DMODULE_DIR2=\"$(libdir)/ivl/@vpidir2@\" MDIR2 = -DMODULE_DIR2=\"$(libdir)/ivl/@vpidir2@\"
endif endif
ifeq (@enable_vvp32@,yes) all: dep vvp@EXEEXT@ libvpi.a
ALL32 = all32
INSTALL32 = install32
UNINSTALL32 = uninstall32
endif
all: dep vvp@EXEEXT@ libvpi.a $(ALL32)
clean: clean:
rm -f *.o *~ parse.cc parse.cc.output parse.h lexor.cc tables.cc rm -f *.o *~ parse.cc parse.cc.output parse.h lexor.cc tables.cc
@ -125,33 +117,6 @@ tables.cc: $(srcdir)/draw_tt.c
./draw_tt > tables.cc ./draw_tt > tables.cc
rm draw_tt@EXEEXT@ rm draw_tt@EXEEXT@
ifeq (@enable_vvp32@,yes)
all32: bin32 vvp32
bin32:
mkdir bin32
bin32/%.o: %.cc
$(CXX) -m32 -DSIZEOF_UNSIGNED_LONG=4 $(CPPFLAGS) $(MDIR2) $(CXXFLAGS) -MD -c $< -o $@
bin32/%.o: %.c
$(CC) -m32 $(CPPFLAGS) $(MDIR2) $(CFLAGS) -MD -c $< -o $@
bin32/lexor.o: lexor.cc parse.h
vvp32: $(addprefix bin32/,$O) bin32/libvpi.a
$(CXX) -m32 $(LDFLAGS) -o vvp32 $(addprefix bin32/,$O) $(LIBS) $(dllib)
bin32/libvpi.a: libvpi.c
$(CC) -m32 $(CPPFLAGS) $(CFLAGS) -o bin32/libvpi.o -c $(srcdir)/libvpi.c
rm -f bin32/libvpi.a
ar cqv bin32/libvpi.a bin32/libvpi.o
$(RANLIB) bin32/libvpi.a
-include $(patsubst bin32/%.o, bin32/%.d, $(addprefix bin32/,$O))
endif
lexor.o: lexor.cc parse.h lexor.o: lexor.cc parse.h
parse.o: parse.cc parse.o: parse.cc
@ -183,13 +148,13 @@ Makefile: Makefile.in config.status
./config.status ./config.status
install: all installdirs $(bindir)/vvp@EXEEXT@ $(libdir64)/libvpi.a $(INSTALL_DOC) $(INSTALL32) install: all installdirs $(bindir)/vvp@EXEEXT@ $(libdir)/libvpi.a $(INSTALL_DOC)
$(bindir)/vvp@EXEEXT@: ./vvp@EXEEXT@ $(bindir)/vvp@EXEEXT@: ./vvp@EXEEXT@
$(INSTALL_PROGRAM) ./vvp@EXEEXT@ $(bindir)/vvp@EXEEXT@ $(INSTALL_PROGRAM) ./vvp@EXEEXT@ $(bindir)/vvp@EXEEXT@
$(libdir64)/libvpi.a : ./libvpi.a $(libdir)/libvpi.a : ./libvpi.a
$(INSTALL_DATA) libvpi.a $(libdir64)/libvpi.a $(INSTALL_DATA) libvpi.a $(libdir)/libvpi.a
$(mandir)/man1/vvp.1: $(srcdir)/vvp.man $(mandir)/man1/vvp.1: $(srcdir)/vvp.man
$(INSTALL_DATA) $(srcdir)/vvp.man $(mandir)/man1/vvp.1 $(INSTALL_DATA) $(srcdir)/vvp.man $(mandir)/man1/vvp.1
@ -198,26 +163,12 @@ $(prefix)/vvp.pdf: vvp.pdf
$(INSTALL_DATA) vvp.pdf $(prefix)/vvp.pdf $(INSTALL_DATA) vvp.pdf $(prefix)/vvp.pdf
installdirs: $(srcdir)/mkinstalldirs installdirs: $(srcdir)/mkinstalldirs
$(srcdir)/mkinstalldirs $(bindir) $(libdir) $(libdir64) $(INSTALL_DOCDIR) $(srcdir)/mkinstalldirs $(bindir) $(libdir) $(libdir) $(INSTALL_DOCDIR)
ifeq (@enable_vvp32@,yes)
install32: all32 $(libdir)/libvpi.a $(bindir)/vvp32
$(libdir)/libvpi.a: bin32/libvpi.a
$(INSTALL_DATA) bin32/libvpi.a $(libdir)/libvpi.a
$(bindir)/vvp32: ./vvp32
$(INSTALL_PROGRAM) ./vvp32 $(bindir)/vvp32
uninstall32:
rm -f $(libdir)/libvpi.a
rm -f $(bindir)/vvp32
endif
uninstall: $(UNINSTALL32) uninstall: $(UNINSTALL32)
rm -f $(bindir)/vvp@EXEEXT@ rm -f $(bindir)/vvp@EXEEXT@
rm -f $(libdir64)/libvpi.a rm -f $(libdir)/libvpi.a
rm -f $(mandir)/man1/vvp.1 $(prefix)/vvp.pdf rm -f $(mandir)/man1/vvp.1 $(prefix)/vvp.pdf
-include $(patsubst %.o, dep/%.d, $O) -include $(patsubst %.o, dep/%.d, $O)

10
vvp/README.txt
View File

@ -140,8 +140,8 @@ The value, then, is appropriate for the data type. For example:
P_123 .param/str "hello", "Hello, World."; P_123 .param/str "hello", "Hello, World.";
The boolean and logic values can also be signed or not. If signed, the The boolean and logic values can also be signed or not. If signed, the
value is preceeded by a '+' character. (Note that the value is 2s value is preceded by a '+' character. (Note that the value is 2s
compliment, so the '+' says only that it is signed, not positive.) complement, so the '+' says only that it is signed, not positive.)
FUNCTOR STATEMENTS: FUNCTOR STATEMENTS:
@ -333,8 +333,8 @@ that arrive through them, while .net nodes reduce strength values to
4-value logic. The .net8 nodes should only be used when strength 4-value logic. The .net8 nodes should only be used when strength
information really is possible. information really is possible.
The <label> is required and is used to locate the net object that is The <label> is required and is used to locate the net object that it
vrepresents. This label does not map to a functor, so only references represents. This label does not map to a functor, so only references
that know they want to access .nets are able to locate the symbol. In that know they want to access .nets are able to locate the symbol. In
particular, this includes behavioral %load and %wait instructions. The particular, this includes behavioral %load and %wait instructions. The
references to net and reg objects are done through the .net label references to net and reg objects are done through the .net label
@ -373,7 +373,7 @@ activates the delay.
ARRAY INDEX STATEMENTS: ARRAY INDEX STATEMENTS:
Variables can be collected into arrays. The words of the array are Variables can be collected into arrays. The words of the array are
declared seperately, this statement collects them together: declared separately, this statement collects them together:
<label> .array "name", <last> <first> ; <label> .array "name", <last> <first> ;

2
vvp/debug.txt
View File

@ -1,7 +1,7 @@
DEBUG AIDS FOR VVP DEBUG AIDS FOR VVP
Debuging vvp can be fiendishly difficult, so there are some built in Debugging vvp can be fiendishly difficult, so there are some built in
debugging aids. These are enabled by setting the environment variable debugging aids. These are enabled by setting the environment variable
VVP_DEBUG to the path to an output file. Then, various detailed debug VVP_DEBUG to the path to an output file. Then, various detailed debug
tools can be enabled as described below. tools can be enabled as described below.

2
xnf.txt
View File

@ -18,7 +18,7 @@ command (man verilog) and the -X switch:
% iverilog -fpart=4010e -fncf=prog.ncf -txnf prog.v % iverilog -fpart=4010e -fncf=prog.ncf -txnf prog.v
This generates from the prog.v Verilog source file the prog.xnf output This generates from the prog.v Verilog source file the prog.xnf output
and the prog.ncf netlist constraints file. The verilog program and the prog.ncf netlist constraints file. The Verilog program
arranges to call the preprocessor and the ivl compiler with all the arranges to call the preprocessor and the ivl compiler with all the
correct switches for generating XNF. correct switches for generating XNF.