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Insert blank line before VHDL process in output

This commit is contained in:
Nick Gasson 2008-08-02 10:45:38 +01:00
parent a60216ec15
commit 752a90dc2f
1 changed files with 2 additions and 2 deletions
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4
tgt-vhdl/vhdl_syntax.cc
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@ -166,7 +166,8 @@ void vhdl_process::emit(std::ostream &of, int level) const
newline(of, level); newline(of, level);
return; return;
} }
newline(of, level);
emit_comment(of, level); emit_comment(of, level);
if (name_.size() > 0) if (name_.size() > 0)
of << name_ << ": "; of << name_ << ": ";
@ -189,7 +190,6 @@ void vhdl_process::emit(std::ostream &of, int level) const
of << "begin"; of << "begin";
stmts_.emit(of, level); stmts_.emit(of, level);
of << "end process;"; of << "end process;";
newline(of, level);
} }
stmt_container::~stmt_container() stmt_container::~stmt_container()