Handle partial sets of conditional clauses.
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c9d480028e
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synth2.cc
39
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.39.2.4 2005/11/13 22:28:48 steve Exp $"
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#ident "$Id: synth2.cc,v 1.39.2.5 2005/11/16 00:38:26 steve Exp $"
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#endif
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# include "config.h"
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@ -510,11 +510,37 @@ bool NetCondit::synth_async(Design*des, NetScope*scope,
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connect(mux->pin_Sel(0), ssig->pin(0));
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for (unsigned idx = 0 ; idx < asig->pin_count() ; idx += 1)
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connect(mux->pin_Data(idx, 1), asig->pin(idx));
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bool return_flag = true;
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for (unsigned idx = 0 ; idx < bsig->pin_count() ; idx += 1)
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connect(mux->pin_Data(idx, 0), bsig->pin(idx));
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/* Connected the clauses to the data inputs of the
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condition. If there are bits unassigned by the case, then
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bind them from the accum bits instead. */
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for (unsigned idx = 0 ; idx < asig->pin_count() ; idx += 1) {
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if (asig->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 1), asig->pin(idx));
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else if (accum->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 1), accum->pin(idx));
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else {
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cerr << get_line()
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<< ": error: Condition true clause "
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<< " does not assign expected outputs." << endl;
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return_flag = false;
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}
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}
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for (unsigned idx = 0 ; idx < bsig->pin_count() ; idx += 1) {
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if (bsig->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 0), bsig->pin(idx));
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else if (accum->pin(idx).is_linked())
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connect(mux->pin_Data(idx, 0), accum->pin(idx));
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else {
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cerr << get_line()
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<< ": error: Condition false clause "
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<< " does not assign expected outputs." << endl;
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return_flag = false;
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}
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}
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for (unsigned idx = 0 ; idx < mux->width() ; idx += 1)
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connect(nex_out->pin(idx), mux->pin_Result(idx));
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@ -1130,6 +1156,9 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.39.2.5 2005/11/16 00:38:26 steve
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* Handle partial sets of conditional clauses.
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*
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* Revision 1.39.2.4 2005/11/13 22:28:48 steve
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* Allow for block output to be set throughout the statements.
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*
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