Parse and elaborate rise/fall/decay times
for gates, and handle the rules for partial lists of times.
This commit is contained in:
steve
parent
dae5916ae1
commit
71d35f32b2
89
PGate.cc
89
PGate.cc
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@ -17,10 +17,92 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: PGate.cc,v 1.1 1999/02/15 02:06:15 steve Exp $"
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#ident "$Id: PGate.cc,v 1.2 1999/08/01 16:34:50 steve Exp $"
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#endif
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# include "PGate.h"
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# include "PExpr.h"
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# include <assert.h>
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PGate::PGate(const string&name,
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svector<PExpr*>*pins,
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const svector<PExpr*>*del)
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: name_(name), pins_(pins)
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{
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for (unsigned idx = 0 ; idx < 3 ; idx += 1)
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delay_[idx] = 0;
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if (del) {
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assert(del->count() <= 3);
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for (unsigned idx = 0 ; idx < del->count() ; idx += 1)
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delay_[idx] = (*del)[idx];
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}
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}
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PGate::PGate(const string&name,
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svector<PExpr*>*pins,
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PExpr*del)
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: name_(name), pins_(pins)
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{
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delay_[0] = del;
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delay_[1] = 0;
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delay_[2] = 0;
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}
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PGate::PGate(const string&name, svector<PExpr*>*pins)
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: name_(name), pins_(pins)
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{
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delay_[0] = 0;
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delay_[1] = 0;
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delay_[2] = 0;
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}
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PGate::~PGate()
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{
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for (unsigned idx = 0 ; idx < 3 ; idx += 1)
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delete delay_[idx];
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}
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const PExpr* PGate::get_delay(unsigned idx) const
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{
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assert(idx < 3);
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return delay_[idx];
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}
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PGAssign::PGAssign(svector<PExpr*>*pins)
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: PGate("", pins)
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{
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assert(pins->count() == 2);
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}
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PGAssign::PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels)
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: PGate("", pins, dels)
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{
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assert(pins->count() == 2);
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}
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PGAssign::~PGAssign()
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{
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}
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PGBuiltin::PGBuiltin(Type t, const string&name,
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svector<PExpr*>*pins,
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svector<PExpr*>*del)
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: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
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{
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}
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PGBuiltin::PGBuiltin(Type t, const string&name,
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svector<PExpr*>*pins,
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PExpr*del)
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: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
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{
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}
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PGBuiltin::~PGBuiltin()
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{
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}
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void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
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{
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@ -33,6 +115,11 @@ void PGBuiltin::set_range(PExpr*msb, PExpr*lsb)
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/*
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* $Log: PGate.cc,v $
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* Revision 1.2 1999/08/01 16:34:50 steve
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* Parse and elaborate rise/fall/decay times
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* for gates, and handle the rules for partial
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* lists of times.
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*
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* Revision 1.1 1999/02/15 02:06:15 steve
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* Elaborate gate ranges.
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*
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41
PGate.h
41
PGate.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: PGate.h,v 1.6 1999/05/29 02:36:17 steve Exp $"
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#ident "$Id: PGate.h,v 1.7 1999/08/01 16:34:50 steve Exp $"
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#endif
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# include "svector.h"
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@ -41,14 +41,19 @@ class Module;
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class PGate : public LineInfo {
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public:
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explicit PGate(const string&name, svector<PExpr*>*pins, long del)
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: name_(name), delay_(del), pins_(pins) { }
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explicit PGate(const string&name, svector<PExpr*>*pins,
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const svector<PExpr*>*del);
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virtual ~PGate() { }
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explicit PGate(const string&name, svector<PExpr*>*pins,
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PExpr*del);
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explicit PGate(const string&name, svector<PExpr*>*pins);
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virtual ~PGate();
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const string& get_name() const { return name_; }
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long get_delay() const { return delay_; }
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const PExpr* get_delay(unsigned idx) const;
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unsigned pin_count() const { return pins_? pins_->count() : 0; }
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const PExpr*pin(unsigned idx) const { return (*pins_)[idx]; }
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@ -60,10 +65,11 @@ class PGate : public LineInfo {
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const svector<PExpr*>* get_pins() const { return pins_; }
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void dump_pins(ostream&out) const;
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void dump_delays(ostream&out) const;
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private:
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const string name_;
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const unsigned long delay_;
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PExpr* delay_[3];
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svector<PExpr*>*pins_;
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private: // not implemented
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@ -78,8 +84,9 @@ class PGate : public LineInfo {
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class PGAssign : public PGate {
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public:
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explicit PGAssign(svector<PExpr*>*pins)
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: PGate("", pins, 0) { assert(pins->count() == 2); }
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explicit PGAssign(svector<PExpr*>*pins);
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explicit PGAssign(svector<PExpr*>*pins, svector<PExpr*>*dels);
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~PGAssign();
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void dump(ostream&out) const;
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virtual void elaborate(Design*des, const string&path) const;
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@ -108,9 +115,12 @@ class PGBuiltin : public PGate {
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public:
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explicit PGBuiltin(Type t, const string&name,
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svector<PExpr*>*pins, long del = 0)
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: PGate(name, pins, del), type_(t), msb_(0), lsb_(0)
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{ }
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svector<PExpr*>*pins,
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svector<PExpr*>*del);
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explicit PGBuiltin(Type t, const string&name,
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svector<PExpr*>*pins,
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PExpr*del);
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~PGBuiltin();
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Type type() const { return type_; }
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void set_range(PExpr*msb, PExpr*lsb);
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@ -138,7 +148,7 @@ class PGModule : public PGate {
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// builds everything all at once.
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explicit PGModule(const string&type, const string&name,
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svector<PExpr*>*pins)
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: PGate(name, pins, 0), type_(type), pins_(0), npins_(0) { }
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: PGate(name, pins), type_(type), pins_(0), npins_(0) { }
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// If the binding of ports is by name, this constructor takes
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// the bindings and stores them for later elaboration.
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@ -148,7 +158,7 @@ class PGModule : public PGate {
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};
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explicit PGModule(const string&type, const string&name,
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bind_t*pins, unsigned npins)
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: PGate(name, 0, 0), type_(type), pins_(pins), npins_(npins) { }
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: PGate(name, 0), type_(type), pins_(pins), npins_(npins) { }
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virtual void dump(ostream&out) const;
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@ -165,6 +175,11 @@ class PGModule : public PGate {
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/*
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* $Log: PGate.h,v $
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* Revision 1.7 1999/08/01 16:34:50 steve
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* Parse and elaborate rise/fall/decay times
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* for gates, and handle the rules for partial
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* lists of times.
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*
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* Revision 1.6 1999/05/29 02:36:17 steve
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* module parameter bind by name.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: design_dump.cc,v 1.33 1999/07/24 02:11:20 steve Exp $"
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#ident "$Id: design_dump.cc,v 1.34 1999/08/01 16:34:50 steve Exp $"
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#endif
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/*
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@ -49,8 +49,8 @@ void NetNet::dump_net(ostream&o, unsigned ind) const
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pin_count() << "]";
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if (local_flag_)
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o << " (local)";
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o << " #(" << delay1() << "," << delay2() << "," << delay3() <<
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") init=";
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o << " #(" << rise_time() << "," << fall_time() << "," <<
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decay_time() << ") init=";
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for (unsigned idx = pin_count() ; idx > 0 ; idx -= 1)
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o << ivalue_[idx-1];
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o << endl;
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@ -70,8 +70,8 @@ void NetMemory::dump(ostream&o, unsigned ind) const
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void NetNode::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "node: ";
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o << typeid(*this).name() << " #(" << delay1()
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<< "," << delay2() << "," << delay3() << ") " << name()
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o << typeid(*this).name() << " #(" << rise_time()
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<< "," << fall_time() << "," << decay_time() << ") " << name()
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<< endl;
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dump_node_pins(o, ind+4);
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@ -185,8 +185,8 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
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o << "xor";
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break;
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}
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o << " #(" << delay1()
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<< "," << delay2() << "," << delay3() << ") " << name()
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o << " #(" << rise_time()
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<< "," << fall_time() << "," << decay_time() << ") " << name()
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<< endl;
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dump_node_pins(o, ind+4);
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@ -227,8 +227,8 @@ void NetUDP::dump_sequ_(ostream&o, unsigned ind) const
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for (unsigned idx = 0 ; idx < ind ; idx += 1)
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tmp += " ";
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o << tmp << "Sequential UDP" << " #(" << delay1() <<
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"," << delay2() << "," << delay3() << ") " << name() <<
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o << tmp << "Sequential UDP" << " #(" << rise_time() <<
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"," << fall_time() << "," << decay_time() << ") " << name() <<
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endl;
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for (FSM_::const_iterator ent = fsm_.begin()
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@ -270,7 +270,7 @@ void NetUDP::dump_sequ_(ostream&o, unsigned ind) const
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void NetUDP::dump_comb_(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "Combinational UDP: ";
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o << " #(" << delay1() << "," << delay2() << "," << delay3() <<
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o << " #(" << rise_time() << "," << fall_time() << "," << decay_time() <<
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") " << name() << endl;
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dump_node_pins(o, ind+4);
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@ -690,6 +690,11 @@ void Design::dump(ostream&o) const
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/*
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* $Log: design_dump.cc,v $
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* Revision 1.34 1999/08/01 16:34:50 steve
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* Parse and elaborate rise/fall/decay times
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* for gates, and handle the rules for partial
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* lists of times.
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*
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* Revision 1.33 1999/07/24 02:11:20 steve
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* Elaborate task input ports.
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*
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183
elaborate.cc
183
elaborate.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: elaborate.cc,v 1.62 1999/07/31 03:16:54 steve Exp $"
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#ident "$Id: elaborate.cc,v 1.63 1999/08/01 16:34:50 steve Exp $"
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#endif
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/*
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@ -232,6 +232,12 @@ void PGAssign::elaborate(Design*des, const string&path) const
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}
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do_assign(des, path, lval, rval);
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if (get_delay(0)) {
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cerr << get_line() << ": Sorry, elaboration does not support"
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" delayed continuous assignments." << endl;
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des->errors += 1;
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}
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}
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/*
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@ -281,6 +287,59 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
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NetLogic**cur = new NetLogic*[count];
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assert(cur);
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/* Calculate the gate delays from the delay expressions
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given in the source. For logic gates, the decay time
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is meaningless because it can never go to high
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impedence. However, the bufif devices can generate
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'bz output, so we will pretend that anything can.
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If only one delay value expression is given (i.e. #5
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nand(foo,...)) then rise, fall and decay times are
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all the same value. If two values are given, rise and
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fall times are use, and the decay time is the minimum
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of the rise and fall times. Finally, if all three
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values are given, they are taken as specified. */
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verinum*dv;
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unsigned long rise_time, fall_time, decay_time;
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if (get_delay(0)) {
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dv = get_delay(0)->eval_const(des, path);
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assert(dv);
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rise_time = dv->as_ulong();
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delete dv;
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if (get_delay(1)) {
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dv = get_delay(1)->eval_const(des, path);
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assert(dv);
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fall_time = dv->as_ulong();
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delete dv;
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if (get_delay(2)) {
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dv = get_delay(2)->eval_const(des, path);
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assert(dv);
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decay_time = dv->as_ulong();
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delete dv;
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} else {
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if (rise_time < fall_time)
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decay_time = rise_time;
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else
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decay_time = fall_time;
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}
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} else {
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assert(get_delay(2) == 0);
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fall_time = rise_time;
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decay_time = rise_time;
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}
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} else {
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rise_time = 0;
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fall_time = 0;
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decay_time = 0;
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}
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/* Now make as many gates as the bit count dictates. Give each
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a unique name, and set the delay times. */
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for (unsigned idx = 0 ; idx < count ; idx += 1) {
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strstream tmp;
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unsigned index;
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@ -325,9 +384,11 @@ void PGBuiltin::elaborate(Design*des, const string&path) const
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break;
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}
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cur[idx]->delay1(get_delay());
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cur[idx]->delay2(get_delay());
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cur[idx]->delay3(get_delay());
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cur[idx]->rise_time(rise_time);
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cur[idx]->fall_time(fall_time);
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cur[idx]->decay_time(decay_time);
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des->add_node(cur[idx]);
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}
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@ -1991,6 +2052,11 @@ Design* elaborate(const map<string,Module*>&modules,
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/*
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* $Log: elaborate.cc,v $
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* Revision 1.63 1999/08/01 16:34:50 steve
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* Parse and elaborate rise/fall/decay times
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* for gates, and handle the rules for partial
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* lists of times.
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*
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* Revision 1.62 1999/07/31 03:16:54 steve
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* move binary operators to derived classes.
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*
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@ -2140,114 +2206,5 @@ Design* elaborate(const map<string,Module*>&modules,
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*
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* Revision 1.22 1999/05/01 02:57:53 steve
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* Handle much more complex event expressions.
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*
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* Revision 1.21 1999/04/29 02:16:26 steve
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* Parse OR of event expressions.
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*
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* Revision 1.20 1999/04/25 00:44:10 steve
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* Core handles subsignal expressions.
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*
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* Revision 1.19 1999/04/19 01:59:36 steve
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* Add memories to the parse and elaboration phases.
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*
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* Revision 1.18 1999/03/15 02:43:32 steve
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* Support more operators, especially logical.
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*
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* Revision 1.17 1999/03/01 03:27:53 steve
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* Prevent the duplicate allocation of ESignal objects.
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*
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* Revision 1.16 1999/02/21 17:01:57 steve
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* Add support for module parameters.
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*
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* Revision 1.15 1999/02/15 02:06:15 steve
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* Elaborate gate ranges.
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*
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* Revision 1.14 1999/02/08 02:49:56 steve
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* Turn the NetESignal into a NetNode so
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* that it can connect to the netlist.
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* Implement the case statement.
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* Convince t-vvm to output code for
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* the case statement.
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*
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* Revision 1.13 1999/02/03 04:20:11 steve
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* Parse and elaborate the Verilog CASE statement.
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*
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* Revision 1.12 1999/02/01 00:26:49 steve
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* Carry some line info to the netlist,
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* Dump line numbers for processes.
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* Elaborate prints errors about port vector
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* width mismatch
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* Emit better handles null statements.
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*
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* Revision 1.11 1999/01/25 05:45:56 steve
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* Add the LineInfo class to carry the source file
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* location of things. PGate, Statement and PProcess.
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*
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* elaborate handles module parameter mismatches,
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* missing or incorrect lvalues for procedural
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* assignment, and errors are propogated to the
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* top of the elaboration call tree.
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*
|
||||
* Attach line numbers to processes, gates and
|
||||
* assignment statements.
|
||||
*
|
||||
* Revision 1.10 1998/12/14 02:01:34 steve
|
||||
* Fully elaborate Sequential UDP behavior.
|
||||
*
|
||||
* Revision 1.9 1998/12/07 04:53:17 steve
|
||||
* Generate OBUF or IBUF attributes (and the gates
|
||||
* to garry them) where a wire is a pad. This involved
|
||||
* figuring out enough of the netlist to know when such
|
||||
* was needed, and to generate new gates and signales
|
||||
* to handle what's missing.
|
||||
*
|
||||
* Revision 1.8 1998/12/02 04:37:13 steve
|
||||
* Add the nobufz function to eliminate bufz objects,
|
||||
* Object links are marked with direction,
|
||||
* constant propagation is more careful will wide links,
|
||||
* Signal folding is aware of attributes, and
|
||||
* the XNF target can dump UDP objects based on LCA
|
||||
* attributes.
|
||||
*
|
||||
* Revision 1.7 1998/12/01 00:42:14 steve
|
||||
* Elaborate UDP devices,
|
||||
* Support UDP type attributes, and
|
||||
* pass those attributes to nodes that
|
||||
* are instantiated by elaboration,
|
||||
* Put modules into a map instead of
|
||||
* a simple list.
|
||||
*
|
||||
* Revision 1.6 1998/11/23 00:20:22 steve
|
||||
* NetAssign handles lvalues as pin links
|
||||
* instead of a signal pointer,
|
||||
* Wire attributes added,
|
||||
* Ability to parse UDP descriptions added,
|
||||
* XNF generates EXT records for signals with
|
||||
* the PAD attribute.
|
||||
*
|
||||
* Revision 1.5 1998/11/21 19:19:44 steve
|
||||
* Give anonymous modules a name when elaborated.
|
||||
*
|
||||
* Revision 1.4 1998/11/11 03:13:04 steve
|
||||
* Handle while loops.
|
||||
*
|
||||
* Revision 1.3 1998/11/09 18:55:34 steve
|
||||
* Add procedural while loops,
|
||||
* Parse procedural for loops,
|
||||
* Add procedural wait statements,
|
||||
* Add constant nodes,
|
||||
* Add XNOR logic gate,
|
||||
* Make vvm output look a bit prettier.
|
||||
*
|
||||
* Revision 1.2 1998/11/07 17:05:05 steve
|
||||
* Handle procedural conditional, and some
|
||||
* of the conditional expressions.
|
||||
*
|
||||
* Elaborate signals and identifiers differently,
|
||||
* allowing the netlist to hold signal information.
|
||||
*
|
||||
* Revision 1.1 1998/11/03 23:28:56 steve
|
||||
* Introduce verilog to CVS.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
|
|||
26
netlist.h
26
netlist.h
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: netlist.h,v 1.52 1999/07/31 03:16:54 steve Exp $"
|
||||
#ident "$Id: netlist.h,v 1.53 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -58,6 +58,13 @@ struct functor_t;
|
|||
* A link can be INPUT, OUTPUT or PASSIVE. An input never drives the
|
||||
* signal, and PASSIVE never receives the value of the signal. Wires
|
||||
* are PASSIVE, for example.
|
||||
*
|
||||
* A NetObj also has delays specified as rise_time, fall_time and
|
||||
* decay_time. The rise and fall time are the times to transition to 1
|
||||
* or 0 values. The decay_time is the time needed to decay to a 'bz
|
||||
* value, or to decay of the net is a trireg. The exact and precise
|
||||
* interpretation of the rise/fall/decay times is typically left to
|
||||
* the target to properly interpret.
|
||||
*/
|
||||
class NetObj {
|
||||
|
||||
|
|
@ -143,13 +150,13 @@ class NetObj {
|
|||
|
||||
unsigned pin_count() const { return npins_; }
|
||||
|
||||
unsigned delay1() const { return delay1_; }
|
||||
unsigned delay2() const { return delay2_; }
|
||||
unsigned delay3() const { return delay3_; }
|
||||
unsigned rise_time() const { return delay1_; }
|
||||
unsigned fall_time() const { return delay2_; }
|
||||
unsigned decay_time() const { return delay3_; }
|
||||
|
||||
void delay1(unsigned d) { delay1_ = d; }
|
||||
void delay2(unsigned d) { delay2_ = d; }
|
||||
void delay3(unsigned d) { delay3_ = d; }
|
||||
void rise_time(unsigned d) { delay1_ = d; }
|
||||
void fall_time(unsigned d) { delay2_ = d; }
|
||||
void decay_time(unsigned d) { delay3_ = d; }
|
||||
|
||||
void set_attributes(const map<string,string>&);
|
||||
string attribute(const string&key) const;
|
||||
|
|
@ -1437,6 +1444,11 @@ extern ostream& operator << (ostream&, NetNet::Type);
|
|||
|
||||
/*
|
||||
* $Log: netlist.h,v $
|
||||
* Revision 1.53 1999/08/01 16:34:50 steve
|
||||
* Parse and elaborate rise/fall/decay times
|
||||
* for gates, and handle the rules for partial
|
||||
* lists of times.
|
||||
*
|
||||
* Revision 1.52 1999/07/31 03:16:54 steve
|
||||
* move binary operators to derived classes.
|
||||
*
|
||||
|
|
|
|||
41
parse.y
41
parse.y
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: parse.y,v 1.54 1999/07/31 19:14:47 steve Exp $"
|
||||
#ident "$Id: parse.y,v 1.55 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "parse_misc.h"
|
||||
|
|
@ -120,9 +120,10 @@ extern void lex_end_table();
|
|||
%type <gate> gate_instance
|
||||
%type <gates> gate_instance_list
|
||||
|
||||
%type <expr> delay delay_opt delay_value delay_value_list
|
||||
%type <expr> expression expr_primary
|
||||
%type <expr> lavalue lpvalue
|
||||
%type <expr> delay_value
|
||||
%type <exprs> delay delay_opt delay_value_list
|
||||
%type <exprs> expression_list
|
||||
|
||||
%type <exprs> range range_opt
|
||||
|
|
@ -247,7 +248,9 @@ defparam_assign_list
|
|||
|
||||
delay
|
||||
: '#' delay_value
|
||||
{ $$ = $2;
|
||||
{ svector<PExpr*>*tmp = new svector<PExpr*>(1);
|
||||
(*tmp)[0] = $2;
|
||||
$$ = tmp;
|
||||
}
|
||||
| '#' '(' delay_value_list ')'
|
||||
{ $$ = $3;
|
||||
|
|
@ -282,11 +285,14 @@ delay_value
|
|||
|
||||
delay_value_list
|
||||
: expression
|
||||
{ $$ = $1; }
|
||||
{ svector<PExpr*>*tmp = new svector<PExpr*>(1);
|
||||
(*tmp)[0] = $1;
|
||||
$$ = tmp;
|
||||
}
|
||||
| delay_value_list ',' expression
|
||||
{ yyerror(@1, "Sorry, delay value lists not supported.");
|
||||
$$ = $1;
|
||||
delete $3;
|
||||
{ svector<PExpr*>*tmp = new svector<PExpr*>(*$1, $3);
|
||||
delete $1;
|
||||
$$ = tmp;
|
||||
}
|
||||
;
|
||||
|
||||
|
|
@ -986,13 +992,9 @@ module_item
|
|||
}
|
||||
}
|
||||
| K_assign delay_opt lavalue '=' expression ';'
|
||||
{ PGAssign*tmp = pform_make_pgassign($3, $5);
|
||||
{ PGAssign*tmp = pform_make_pgassign($3, $5, $2);
|
||||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
if ($2) {
|
||||
yyerror(@2, "Sorry, assign delays not supported.");
|
||||
delete $2;
|
||||
}
|
||||
}
|
||||
| K_assign error '=' expression ';'
|
||||
| K_always statement
|
||||
|
|
@ -1051,18 +1053,17 @@ module_item_list
|
|||
net_decl_assign
|
||||
: IDENTIFIER '=' expression
|
||||
{ PEIdent*id = new PEIdent($1);
|
||||
PGAssign*tmp = pform_make_pgassign(id, $3);
|
||||
PGAssign*tmp = pform_make_pgassign(id, $3, 0);
|
||||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
$$ = $1;
|
||||
}
|
||||
| delay IDENTIFIER '=' expression
|
||||
{ PEIdent*id = new PEIdent($2);
|
||||
PGAssign*tmp = pform_make_pgassign(id, $4);
|
||||
PGAssign*tmp = pform_make_pgassign(id, $4, $1);
|
||||
tmp->set_file(@2.text);
|
||||
tmp->set_lineno(@2.first_line);
|
||||
$$ = $2;
|
||||
yyerror(@1, "Sorry, net assign delay not supported.");
|
||||
}
|
||||
;
|
||||
|
||||
|
|
@ -1456,7 +1457,10 @@ statement
|
|||
yyerror(@3, "Error in while loop condition.");
|
||||
}
|
||||
| delay statement_opt
|
||||
{ PDelayStatement*tmp = new PDelayStatement($1, $2);
|
||||
{ PExpr*del = (*$1)[0];
|
||||
if ($1->count() != 1)
|
||||
yyerror(@1, "Sorry, delay lists not supported here.");
|
||||
PDelayStatement*tmp = new PDelayStatement(del, $2);
|
||||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
$$ = tmp;
|
||||
|
|
@ -1484,7 +1488,10 @@ statement
|
|||
$$ = tmp;
|
||||
}
|
||||
| lpvalue '=' delay expression ';'
|
||||
{ PAssign*tmp = new PAssign($1,$3,$4);
|
||||
{ PExpr*del = (*$3)[0];
|
||||
if ($3->count() != 1)
|
||||
yyerror(@1, "Sorry, delay lists not supported here.");
|
||||
PAssign*tmp = new PAssign($1,del,$4);
|
||||
tmp->set_file(@1.text);
|
||||
tmp->set_lineno(@1.first_line);
|
||||
$$ = tmp;
|
||||
|
|
|
|||
30
pform.cc
30
pform.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: pform.cc,v 1.35 1999/07/31 19:15:21 steve Exp $"
|
||||
#ident "$Id: pform.cc,v 1.36 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "compiler.h"
|
||||
|
|
@ -267,7 +267,7 @@ void pform_make_udp(const char*name, list<string>*parms,
|
|||
* gates and calls the pform_makegate function to make the individual gate.
|
||||
*/
|
||||
void pform_makegate(PGBuiltin::Type type,
|
||||
unsigned long delay_val,
|
||||
svector<PExpr*>* delay,
|
||||
const lgate&info)
|
||||
{
|
||||
if (info.parms_by_name) {
|
||||
|
|
@ -277,7 +277,7 @@ void pform_makegate(PGBuiltin::Type type,
|
|||
return;
|
||||
}
|
||||
|
||||
PGBuiltin*cur = new PGBuiltin(type, info.name, info.parms, delay_val);
|
||||
PGBuiltin*cur = new PGBuiltin(type, info.name, info.parms, delay);
|
||||
if (info.range[0])
|
||||
cur->set_range(info.range[0], info.range[1]);
|
||||
|
||||
|
|
@ -288,13 +288,10 @@ void pform_makegate(PGBuiltin::Type type,
|
|||
}
|
||||
|
||||
void pform_makegates(PGBuiltin::Type type,
|
||||
PExpr*delay, svector<lgate>*gates)
|
||||
svector<PExpr*>*delay, svector<lgate>*gates)
|
||||
{
|
||||
unsigned long delay_val = delay? evaluate_delay(delay) : 0;
|
||||
delete delay;
|
||||
|
||||
for (unsigned idx = 0 ; idx < gates->count() ; idx += 1) {
|
||||
pform_makegate(type, delay_val, (*gates)[idx]);
|
||||
pform_makegate(type, delay, (*gates)[idx]);
|
||||
}
|
||||
|
||||
delete gates;
|
||||
|
|
@ -370,12 +367,20 @@ void pform_make_modgates(const string&type, svector<lgate>*gates)
|
|||
delete gates;
|
||||
}
|
||||
|
||||
PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval)
|
||||
PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval,
|
||||
svector<PExpr*>*del)
|
||||
{
|
||||
svector<PExpr*>*wires = new svector<PExpr*>(2);
|
||||
(*wires)[0] = lval;
|
||||
(*wires)[1] = rval;
|
||||
PGAssign*cur = new PGAssign(wires);
|
||||
|
||||
PGAssign*cur;
|
||||
|
||||
if (del == 0)
|
||||
cur = new PGAssign(wires);
|
||||
else
|
||||
cur = new PGAssign(wires, del);
|
||||
|
||||
pform_cur_module->add_gate(cur);
|
||||
return cur;
|
||||
}
|
||||
|
|
@ -657,6 +662,11 @@ int pform_parse(const char*path, map<string,Module*>&modules,
|
|||
|
||||
/*
|
||||
* $Log: pform.cc,v $
|
||||
* Revision 1.36 1999/08/01 16:34:50 steve
|
||||
* Parse and elaborate rise/fall/decay times
|
||||
* for gates, and handle the rules for partial
|
||||
* lists of times.
|
||||
*
|
||||
* Revision 1.35 1999/07/31 19:15:21 steve
|
||||
* misspelled comment.
|
||||
*
|
||||
|
|
|
|||
12
pform.h
12
pform.h
|
|
@ -19,7 +19,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: pform.h,v 1.25 1999/07/31 19:14:47 steve Exp $"
|
||||
#ident "$Id: pform.h,v 1.26 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "netlist.h"
|
||||
|
|
@ -138,13 +138,14 @@ extern bool pform_expression_is_constant(const PExpr*);
|
|||
* name) and connects it to the specified wires.
|
||||
*/
|
||||
extern void pform_makegates(PGBuiltin::Type type,
|
||||
PExpr*delay,
|
||||
svector<PExpr*>*delay,
|
||||
svector<lgate>*gates);
|
||||
|
||||
extern void pform_make_modgates(const string&type, svector<lgate>*gates);
|
||||
|
||||
/* Make a continuous assignment node, with optional bit- or part- select. */
|
||||
extern PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval);
|
||||
extern PGAssign* pform_make_pgassign(PExpr*lval, PExpr*rval,
|
||||
svector<PExpr*>*delays);
|
||||
|
||||
|
||||
/* Given a port type and a list of names, make a list of wires that
|
||||
|
|
@ -166,6 +167,11 @@ extern void pform_dump(ostream&out, Module*mod);
|
|||
|
||||
/*
|
||||
* $Log: pform.h,v $
|
||||
* Revision 1.26 1999/08/01 16:34:50 steve
|
||||
* Parse and elaborate rise/fall/decay times
|
||||
* for gates, and handle the rules for partial
|
||||
* lists of times.
|
||||
*
|
||||
* Revision 1.25 1999/07/31 19:14:47 steve
|
||||
* Add functions up to elaboration (Ed Carter)
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: pform_dump.cc,v 1.31 1999/07/31 19:14:47 steve Exp $"
|
||||
#ident "$Id: pform_dump.cc,v 1.32 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -209,10 +209,23 @@ void PGate::dump_pins(ostream&out) const
|
|||
}
|
||||
}
|
||||
|
||||
void PGate::dump_delays(ostream&out) const
|
||||
{
|
||||
if (delay_[0] && delay_[1] && delay_[2])
|
||||
out << "#(" << *delay_[0] << "," << *delay_[1] << "," <<
|
||||
*delay_[2] << ")";
|
||||
else if (delay_[0])
|
||||
out << "#" << *delay_[0];
|
||||
else
|
||||
out << "#0";
|
||||
|
||||
}
|
||||
|
||||
void PGate::dump(ostream&out) const
|
||||
{
|
||||
out << " " << typeid(*this).name() << " #"
|
||||
<< get_delay() << " " << get_name() << "(";
|
||||
out << " " << typeid(*this).name() << " ";
|
||||
dump_delays(out);
|
||||
out << " " << get_name() << "(";
|
||||
dump_pins(out);
|
||||
out << ");" << endl;
|
||||
|
||||
|
|
@ -220,26 +233,29 @@ void PGate::dump(ostream&out) const
|
|||
|
||||
void PGAssign::dump(ostream&out) const
|
||||
{
|
||||
out << " assign " << *pin(0) << " = " << *pin(1) << ";" << endl;
|
||||
out << " assign ";
|
||||
dump_delays(out);
|
||||
out << " " << *pin(0) << " = " << *pin(1) << ";" << endl;
|
||||
}
|
||||
|
||||
void PGBuiltin::dump(ostream&out) const
|
||||
{
|
||||
switch (type()) {
|
||||
case PGBuiltin::BUFIF0:
|
||||
out << " bufif0 #";
|
||||
out << " bufif0 ";
|
||||
break;
|
||||
case PGBuiltin::BUFIF1:
|
||||
out << " bufif1 #";
|
||||
out << " bufif1 ";
|
||||
break;
|
||||
case PGBuiltin::NAND:
|
||||
out << " nand #";
|
||||
out << " nand ";
|
||||
break;
|
||||
default:
|
||||
out << " builtin gate #";
|
||||
out << " builtin gate ";
|
||||
}
|
||||
|
||||
out << get_delay() << " " << get_name();
|
||||
dump_delays(out);
|
||||
out << " " << get_name();
|
||||
|
||||
if (msb_) {
|
||||
out << " [" << *msb_ << ":" << *lsb_ << "]";
|
||||
|
|
@ -578,6 +594,11 @@ void PUdp::dump(ostream&out) const
|
|||
|
||||
/*
|
||||
* $Log: pform_dump.cc,v $
|
||||
* Revision 1.32 1999/08/01 16:34:50 steve
|
||||
* Parse and elaborate rise/fall/decay times
|
||||
* for gates, and handle the rules for partial
|
||||
* lists of times.
|
||||
*
|
||||
* Revision 1.31 1999/07/31 19:14:47 steve
|
||||
* Add functions up to elaboration (Ed Carter)
|
||||
*
|
||||
|
|
|
|||
13
t-verilog.cc
13
t-verilog.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: t-verilog.cc,v 1.6 1999/07/03 02:12:52 steve Exp $"
|
||||
#ident "$Id: t-verilog.cc,v 1.7 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
@ -78,8 +78,8 @@ void target_verilog::signal(ostream&os, const NetNet*net)
|
|||
if (net->pin_count() > 1)
|
||||
os << " [" << net->msb() << ":" << net->lsb() << "]";
|
||||
|
||||
if (net->delay1())
|
||||
os << " #" << net->delay1();
|
||||
if (net->rise_time())
|
||||
os << " #" << net->rise_time();
|
||||
|
||||
os << " " << mangle(net->name()) << ";" << endl;
|
||||
}
|
||||
|
|
@ -111,7 +111,7 @@ void target_verilog::logic(ostream&os, const NetLogic*net)
|
|||
break;
|
||||
}
|
||||
|
||||
os << " #" << net->delay1() << " " << mangle(net->name()) << "(";
|
||||
os << " #" << net->rise_time() << " " << mangle(net->name()) << "(";
|
||||
|
||||
unsigned sidx;
|
||||
const NetNet*sig = find_link_signal(net, 0, sidx);
|
||||
|
|
@ -271,6 +271,11 @@ const struct target tgt_verilog = {
|
|||
|
||||
/*
|
||||
* $Log: t-verilog.cc,v $
|
||||
* Revision 1.7 1999/08/01 16:34:50 steve
|
||||
* Parse and elaborate rise/fall/decay times
|
||||
* for gates, and handle the rules for partial
|
||||
* lists of times.
|
||||
*
|
||||
* Revision 1.6 1999/07/03 02:12:52 steve
|
||||
* Elaborate user defined tasks.
|
||||
*
|
||||
|
|
|
|||
25
t-vvm.cc
25
t-vvm.cc
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#if !defined(WINNT)
|
||||
#ident "$Id: t-vvm.cc,v 1.32 1999/07/18 21:17:51 steve Exp $"
|
||||
#ident "$Id: t-vvm.cc,v 1.33 1999/08/01 16:34:50 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include <iostream>
|
||||
|
|
@ -530,36 +530,36 @@ void target_vvm::logic(ostream&os, const NetLogic*gate)
|
|||
switch (gate->type()) {
|
||||
case NetLogic::AND:
|
||||
os << "static vvm_and" << "<" << gate->pin_count()-1 <<
|
||||
"," << gate->delay1() << "> ";
|
||||
"," << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::BUFIF0:
|
||||
os << "static vvm_bufif0<" << gate->delay1() << "> ";
|
||||
os << "static vvm_bufif0<" << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::BUFIF1:
|
||||
os << "static vvm_bufif1<" << gate->delay1() << "> ";
|
||||
os << "static vvm_bufif1<" << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::NAND:
|
||||
os << "static vvm_nand" << "<" << gate->pin_count()-1 <<
|
||||
"," << gate->delay1() << "> ";
|
||||
"," << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::NOR:
|
||||
os << "static vvm_nor" << "<" << gate->pin_count()-1 <<
|
||||
"," << gate->delay1() << "> ";
|
||||
"," << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::NOT:
|
||||
os << "static vvm_not" << "<" << gate->delay1() << "> ";
|
||||
os << "static vvm_not" << "<" << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::OR:
|
||||
os << "static vvm_or" << "<" << gate->pin_count()-1 <<
|
||||
"," << gate->delay1() << "> ";
|
||||
"," << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::XNOR:
|
||||
os << "static vvm_xnor" << "<" << gate->pin_count()-1 <<
|
||||
"," << gate->delay1() << "> ";
|
||||
"," << gate->rise_time() << "> ";
|
||||
break;
|
||||
case NetLogic::XOR:
|
||||
os << "static vvm_xor" << "<" << gate->pin_count()-1 <<
|
||||
"," << gate->delay1() << "> ";
|
||||
"," << gate->rise_time() << "> ";
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1287,6 +1287,11 @@ extern const struct target tgt_vvm = {
|
|||
};
|
||||
/*
|
||||
* $Log: t-vvm.cc,v $
|
||||
* Revision 1.33 1999/08/01 16:34:50 steve
|
||||
* Parse and elaborate rise/fall/decay times
|
||||
* for gates, and handle the rules for partial
|
||||
* lists of times.
|
||||
*
|
||||
* Revision 1.32 1999/07/18 21:17:51 steve
|
||||
* Add support for CE input to XNF DFF, and do
|
||||
* complete cleanup of replaced design nodes.
|
||||
|
|
|
|||
Loading…
Reference in New Issue