Verilog 2001 attriubtes on nets/wires.

ivl.def

@@ -121,6 +121,8 @@ ivl_scope_type
 ivl_scope_tname
 
 ivl_signal_attr
+ivl_signal_attr_cnt
+ivl_signal_attr_val
 ivl_signal_pin
 ivl_signal_pins
 ivl_signal_port

ivl_target.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: ivl_target.h,v 1.95 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: ivl_target.h,v 1.96 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 #ifdef __cplusplus
@@ -918,6 +918,9 @@ extern const char* ivl_signal_name(ivl_signal_t net);
 extern const char* ivl_signal_basename(ivl_signal_t net);
 extern const char* ivl_signal_attr(ivl_signal_t net, const char*key);
 
+extern unsigned        ivl_signal_attr_cnt(ivl_signal_t net);
+extern ivl_attribute_t ivl_signal_attr_val(ivl_signal_t net, unsigned idx);
+
 
 /*
  * These functions get information about a process. A process is
@@ -1034,6 +1037,9 @@ _END_DECL
 
 /*
  * $Log: ivl_target.h,v $
+ * Revision 1.96  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.95  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

parse.y

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: parse.y,v 1.152 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: parse.y,v 1.153 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include "config.h"
@@ -1342,19 +1342,30 @@ range_delay : range_opt delay3_opt
 
 
 module_item
-	: net_type range_delay list_of_identifiers ';'
+	: attribute_list_opt net_type range_delay list_of_identifiers ';'
-		{ pform_makewire(@1, $2.range, $3, $1);
+		{ pform_makewire(@2, $3.range, $4, $2, $1);
-		  if ($2.delay != 0) {
+		  if ($3.delay != 0) {
-			yyerror(@2, "sorry: net delays not supported.");
+			yyerror(@3, "sorry: net delays not supported.");
-			delete $2.delay;
+			delete $3.delay;
+		  }
+		  if ($1) delete $1;
+		}
+	| attribute_list_opt net_type range_delay net_decl_assigns ';'
+		{ pform_makewire(@2, $3.range, $3.delay, str_strength,
+				 $4, $2);
+		  if ($1) {
+			yyerror(@3, "sorry: Attributes not supported "
+				"on net declaration assignments.");
+			delete $1;
 		  }
 		}
-	| net_type range_delay net_decl_assigns ';'
+	| attribute_list_opt net_type drive_strength net_decl_assigns ';'
-		{ pform_makewire(@1, $2.range, $2.delay, str_strength,
+		{ pform_makewire(@2, 0, 0, $3, $4, $2);
-				 $3, $1);
+		  if ($1) {
-		}
+			yyerror(@3, "sorry: Attributes not supported "
-	| net_type drive_strength net_decl_assigns ';'
+				"on net declaration assignments.");
-		{ pform_makewire(@1, 0, 0, $2, $3, $1);
+			delete $1;
+		  }
 		}
 	| K_trireg charge_strength_opt range_delay list_of_identifiers ';'
 		{ yyerror(@1, "sorry: trireg nets not supported.");
@@ -1958,11 +1969,11 @@ range_or_type_opt
      so that bit ranges can be assigned. */
 register_variable
 	: IDENTIFIER
-		{ pform_makewire(@1, $1, NetNet::REG);
+		{ pform_makewire(@1, $1, NetNet::REG, 0);
 		  $$ = $1;
 		}
 	| IDENTIFIER '=' expression
-		{ pform_makewire(@1, $1, NetNet::REG);
+		{ pform_makewire(@1, $1, NetNet::REG, 0);
 		  if (! pform_expression_is_constant($3))
 			yyerror(@3, "error: register declaration assignment"
 				" value must be a constant expression.");
@@ -1970,7 +1981,7 @@ register_variable
 		  $$ = $1;
 		}
 	| IDENTIFIER '[' expression ':' expression ']'
-		{ pform_makewire(@1, $1, NetNet::REG);
+		{ pform_makewire(@1, $1, NetNet::REG, 0);
 		  if (! pform_expression_is_constant($3))
 			yyerror(@3, "error: msb of register range must be constant.");
 		  if (! pform_expression_is_constant($5))

pform.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: pform.cc,v 1.96 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: pform.cc,v 1.97 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include "config.h"
@@ -866,7 +866,8 @@ void pform_module_define_port(const struct vlltype&li,
  * do check to see if the name has already been declared, as this
  * function is called for every declaration.
  */
-void pform_makewire(const vlltype&li, const char*nm, NetNet::Type type)
+void pform_makewire(const vlltype&li, const char*nm,
+		    NetNet::Type type, svector<named_pexpr_t*>*attr)
 {
       hname_t name = hier_name(nm);
       PWire*cur = pform_cur_module->get_wire(name);
@@ -896,19 +897,28 @@ void pform_makewire(const vlltype&li, const char*nm, NetNet::Type type)
       cur = new PWire(name, type, NetNet::NOT_A_PORT);
       cur->set_file(li.text);
       cur->set_lineno(li.first_line);
+
+      if (attr) {
+	    for (unsigned idx = 0 ;  idx < attr->count() ;  idx += 1) {
+		  named_pexpr_t*tmp = (*attr)[idx];
+		  cur->attributes[tmp->name] = tmp->parm;
+	    }
+      }
+
       pform_cur_module->add_wire(cur);
 }
 
 void pform_makewire(const vlltype&li,
 		    svector<PExpr*>*range,
 		    list<char*>*names,
-		    NetNet::Type type)
+		    NetNet::Type type,
+		    svector<named_pexpr_t*>*attr)
 {
       for (list<char*>::iterator cur = names->begin()
 		 ; cur != names->end()
 		 ; cur ++ ) {
 	    char*txt = *cur;
-	    pform_makewire(li, txt, type);
+	    pform_makewire(li, txt, type, attr);
 	    pform_set_net_range(txt, range, false);
 	    free(txt);
       }
@@ -931,7 +941,7 @@ void pform_makewire(const vlltype&li,
       while (first) {
 	    net_decl_assign_t*next = first->next;
 
-	    pform_makewire(li, first->name, type);
+	    pform_makewire(li, first->name, type, 0);
 	    pform_set_net_range(first->name, range, false);
 
 	    hname_t name = hier_name(first->name);
@@ -1327,6 +1337,9 @@ int pform_parse(const char*path, FILE*file)
 
 /*
  * $Log: pform.cc,v $
+ * Revision 1.97  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.96  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

pform.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: pform.h,v 1.58 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: pform.h,v 1.59 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include  "netlist.h"
@@ -153,12 +153,14 @@ extern void pform_pop_scope();
  * go into a module that is currently opened.
  */
 extern void pform_makewire(const struct vlltype&li, const char*name,
-			   NetNet::Type type = NetNet::IMPLICIT);
+			   NetNet::Type type,
+			   svector<named_pexpr_t*>*attr);
 
 extern void pform_makewire(const struct vlltype&li,
 			   svector<PExpr*>*range,
 			   list<char*>*names,
-			   NetNet::Type type);
+			   NetNet::Type type,
+			   svector<named_pexpr_t*>*attr);
 extern void pform_makewire(const struct vlltype&li,
 			   svector<PExpr*>*range,
 			   svector<PExpr*>*delay,
@@ -248,6 +250,9 @@ extern void pform_dump(ostream&out, Module*mod);
 
 /*
  * $Log: pform.h,v $
+ * Revision 1.59  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.58  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

pform_dump.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: pform_dump.cc,v 1.72 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: pform_dump.cc,v 1.73 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include "config.h"
@@ -254,8 +254,10 @@ void PWire::dump(ostream&out) const
       for (map<string,PExpr*>::const_iterator idx = attributes.begin()
 		 ; idx != attributes.end()
 		 ; idx ++) {
-	    out << "        " << (*idx).first << " = \"" <<
+	    out << "        " << (*idx).first;
-		  *(*idx).second << "\"" << endl;
+	    if ((*idx).second)
+		  out << " = " << *(*idx).second;
+	    out << endl;
       }
 }
 
@@ -809,21 +811,26 @@ void PUdp::dump(ostream&out) const
 	    out << "    initial " << ports[0] << " = 1'b" << initial
 		<< ";" << endl;
 
-      out << "endprimitive" << endl;
-
 	// Dump the attributes for the primitive as attribute
 	// statements.
       for (map<string,PExpr*>::const_iterator idx = attributes.begin()
 		 ; idx != attributes.end()
 		 ; idx ++) {
-	    out << "$attribute(" << name_ << ", \"" << (*idx).first <<
+	    out << "    attribute " << (*idx).first;
-		  "\", \"" << *(*idx).second << "\")" << endl;
+	    if ((*idx).second)
+		  out << " = " << *(*idx).second;
+	    out << endl;
       }
+
+      out << "endprimitive" << endl;
 }
 
 
 /*
  * $Log: pform_dump.cc,v $
+ * Revision 1.73  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.72  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

t-dll-api.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll-api.cc,v 1.78 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: t-dll-api.cc,v 1.79 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include "config.h"
@@ -1127,20 +1127,30 @@ extern "C" const char* ivl_scope_tname(ivl_scope_t net)
 
 extern "C" const char* ivl_signal_attr(ivl_signal_t net, const char*key)
 {
-      if (net->nattr_ == 0)
+      if (net->nattr == 0)
 	    return 0;
 
-      assert(net->akey_);
+      for (unsigned idx = 0 ;  idx < net->nattr ;  idx += 1)
-      assert(net->aval_);
 
-      for (unsigned idx = 0 ;  idx < net->nattr_ ;  idx += 1)
+	    if (strcmp(key, net->attr[idx].key) == 0)
-
+		  return net->attr[idx].type == IVL_ATT_STR
-	    if (strcmp(key, net->akey_[idx]) == 0)
+			? net->attr[idx].val.str
-		  return net->aval_[idx];
+			: 0;
 
       return 0;
 }
 
+extern "C" unsigned ivl_signal_attr_cnt(ivl_signal_t net)
+{
+      return net->nattr;
+}
+
+extern "C" ivl_attribute_t ivl_signal_attr_val(ivl_signal_t net, unsigned idx)
+{
+      assert(idx < net->nattr);
+      return net->attr + idx;
+}
+
 extern "C" const char* ivl_signal_basename(ivl_signal_t net)
 {
       return basename(net->scope_, net->name_);
@@ -1509,6 +1519,9 @@ extern "C" ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net)
 
 /*
  * $Log: t-dll-api.cc,v $
+ * Revision 1.79  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.78  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

t-dll.cc

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll.cc,v 1.82 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: t-dll.cc,v 1.83 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include "config.h"
@@ -135,6 +135,35 @@ static void drive_from_link(const Link&lnk, ivl_drive_t&drv0, ivl_drive_t&drv1)
       }
 }
 
+static ivl_attribute_s* fill_in_attributes(const NetObj*net)
+{
+      ivl_attribute_s*attr;
+      unsigned nattr = net->nattr();
+
+      if (nattr == 0)
+	    return 0;
+
+      attr = new struct ivl_attribute_s[nattr];
+
+      for (unsigned idx = 0 ;  idx < nattr ;  idx += 1) {
+	    verinum tmp = net->attr_value(idx);
+	    attr[idx].key = strdup(net->attr_key(idx));
+	    if (tmp.is_string()) {
+		  attr[idx].type = IVL_ATT_STR;
+		  attr[idx].val.str = strdup(tmp.as_string().c_str());
+
+	    } else if (tmp == verinum()) {
+		  attr[idx].type = IVL_ATT_VOID;
+
+	    } else {
+		  attr[idx].type = IVL_ATT_NUM;
+		  attr[idx].val.num = tmp.as_long();
+	    }
+      }
+
+      return attr;
+}
+
 /*
  * This function locates an ivl_scope_t object that matches the
  * NetScope object. The search works by looking for the parent scope,
@@ -476,29 +505,7 @@ static void logic_attributes(struct ivl_net_logic_s *obj,
 			     const NetNode*net)
 {
       obj->nattr = net->nattr();
-      if (obj->nattr > 0) {
+      obj->attr = fill_in_attributes(net);
-	    obj->attr = new struct ivl_attribute_s[obj->nattr];
-	    for (unsigned idx = 0 ;  idx < obj->nattr ;  idx += 1) {
-		  verinum tmp = net->attr_value(idx);
-		  obj->attr[idx].key = strdup(net->attr_key(idx));
-		  if (tmp.is_string()) {
-			obj->attr[idx].type = IVL_ATT_STR;
-			obj->attr[idx].val.str =
-			      strdup(tmp.as_string().c_str());
-
-		  } else if (tmp == verinum()) {
-			obj->attr[idx].type = IVL_ATT_VOID;
-
-		  } else {
-			obj->attr[idx].type = IVL_ATT_NUM;
-			obj->attr[idx].val.num = tmp.as_long();
-		  }
-	    }
-
-
-      } else {
-	    obj->attr = 0;
-      }
 }
 
 /*
@@ -1886,13 +1893,9 @@ void dll_target::signal(const NetNet*net)
 	    break;
       }
 
-      obj->nattr_ = net->nattr();
+      obj->nattr = net->nattr();
-      obj->akey_  = new char*[obj->nattr_];
+      obj->attr = fill_in_attributes(net);
-      obj->aval_  = new char*[obj->nattr_];
+
-      for (unsigned idx = 0 ;  idx < obj->nattr_ ;  idx += 1) {
-	    obj->akey_[idx] = strdup(net->attr_key(idx));
-	    obj->aval_[idx] = strdup(net->attr_value(idx).as_string().c_str());
-      }
 
 	/* Get the nexus objects for all the pins of the signal. If
 	   the signal has only one pin, then write the single
@@ -1943,6 +1946,9 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
 
 /*
  * $Log: t-dll.cc,v $
+ * Revision 1.83  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.82  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

t-dll.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: t-dll.h,v 1.77 2002/05/23 03:08:51 steve Exp $"
+#ident "$Id: t-dll.h,v 1.78 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include  "target.h"
@@ -506,9 +506,8 @@ struct ivl_signal_s {
 	    ivl_nexus_t*pins_;
       } n;
 
-      char**akey_;
+      struct ivl_attribute_s*attr;
-      char**aval_;
+      unsigned nattr;
-      unsigned nattr_;
 };
 
 /*
@@ -598,6 +597,9 @@ struct ivl_statement_s {
 
 /*
  * $Log: t-dll.h,v $
+ * Revision 1.78  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.77  2002/05/23 03:08:51  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute

tgt-stub/stub.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #if !defined(WINNT) && !defined(macintosh)
-#ident "$Id: stub.c,v 1.58 2002/05/23 03:08:52 steve Exp $"
+#ident "$Id: stub.c,v 1.59 2002/05/24 04:36:23 steve Exp $"
 #endif
 
 # include "config.h"
@@ -507,6 +507,23 @@ static void show_signal(ivl_signal_t net)
 		  }
 	    }
       }
+
+      for (pin = 0 ;  pin < ivl_signal_attr_cnt(net) ;  pin += 1) {
+	    ivl_attribute_t atr = ivl_signal_attr_val(net, pin);
+
+	    switch (atr->type) {
+		case IVL_ATT_STR:
+		  fprintf(out, "    %s = %s\n", atr->key, atr->val.str);
+		  break;
+		case IVL_ATT_NUM:
+		  fprintf(out, "    %s = %ld\n", atr->key, atr->val.num);
+		  break;
+		case IVL_ATT_VOID:
+		  fprintf(out, "    %s\n", atr->key);
+		  break;
+	    }
+      }
+
 }
 
 static void show_logic(ivl_net_logic_t net)
@@ -646,6 +663,9 @@ int target_design(ivl_design_t des)
 
 /*
  * $Log: stub.c,v $
+ * Revision 1.59  2002/05/24 04:36:23  steve
+ *  Verilog 2001 attriubtes on nets/wires.
+ *
  * Revision 1.58  2002/05/23 03:08:52  steve
  *  Add language support for Verilog-2001 attribute
  *  syntax. Hook this support into existing $attribute