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iverilog
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hex numbers exactly 4 bits.

This commit is contained in:
steve 1999-06-12 23:16:08 +00:00
parent 29da349106
commit 7000a56845
1 changed files with 2 additions and 2 deletions
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4
lexor.lex
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@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: lexor.lex,v 1.19 1999/06/12 20:35:27 steve Exp $"
#ident "$Id: lexor.lex,v 1.20 1999/06/12 23:16:08 steve Exp $"
#endif
//# define YYSTYPE lexval
@ -469,7 +469,7 @@ static verinum*make_sized_hex(const char*txt)
unsigned idx = 0;
char*eptr = ptr + strlen(ptr) - 1;
while ((eptr > ptr) && (idx < (size-4))) {
while ((eptr > ptr) && (idx <= (size-4))) {
switch (*eptr) {
case 'x':
bits[idx++] = verinum::Vx;