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Remove the useless vvm_simulation class.

This commit is contained in:
steve 1999-12-12 19:47:54 +00:00
parent 76655ce2bb
commit 6be5421c8a
10 changed files with 231 additions and 424 deletions
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147
t-vvm.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: t-vvm.cc,v 1.89 1999/12/12 06:03:14 steve Exp $" #ident "$Id: t-vvm.cc,v 1.90 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include <iostream> # include <iostream>
@ -315,7 +315,7 @@ void vvm_proc_rval::expr_ufunc(const NetEUFunc*expr)
} }
/* Make the function call. */ /* Make the function call. */
os_ << " " << mangle(expr->name()) << "(sim_);" << endl; os_ << " " << mangle(expr->name()) << "();" << endl;
/* Save the return value in a temporary. */ /* Save the return value in a temporary. */
result = make_temp(); result = make_temp();
@ -612,11 +612,11 @@ void target_vvm::start_design(ostream&os, const Design*mod)
os << "static struct __vpiStringConst string_table[];" << endl; os << "static struct __vpiStringConst string_table[];" << endl;
os << "static struct __vpiNumberConst number_table[];" << endl; os << "static struct __vpiNumberConst number_table[];" << endl;
init_code << "static void design_init(vvm_simulation&sim)" << endl; init_code << "static void design_init()" << endl;
init_code << "{" << endl; init_code << "{" << endl;
init_code << " vpip_init_simulation();" init_code << " vpip_init_simulation();"
<< endl; << endl;
start_code << "static void design_start(vvm_simulation&sim)" << endl; start_code << "static void design_start()" << endl;
start_code << "{" << endl; start_code << "{" << endl;
} }
@ -701,15 +701,14 @@ void target_vvm::end_design(ostream&os, const Design*mod)
os << " vvm_set_module_path(\"" << vpi_module_path << os << " vvm_set_module_path(\"" << vpi_module_path <<
"\");" << endl; "\");" << endl;
os << " vvm_load_vpi_module(\"system.vpi\");" << endl; os << " vvm_load_vpi_module(\"system.vpi\");" << endl;
os << " vvm_simulation sim;" << endl; os << " design_init();" << endl;
os << " design_init(sim);" << endl; os << " design_start();" << endl;
os << " design_start(sim);" << endl;
for (unsigned idx = 0 ; idx < process_counter ; idx += 1) for (unsigned idx = 0 ; idx < process_counter ; idx += 1)
os << " thread" << (idx+1) << "_t thread_" << os << " thread" << (idx+1) << "_t thread_" <<
(idx+1) << "(&sim);" << endl; (idx+1) << ";" << endl;
os << " sim.run();" << endl; os << " vpip_simulation_run();" << endl;
os << "}" << endl; os << "}" << endl;
} }
@ -799,8 +798,8 @@ void target_vvm::task_def(ostream&os, const NetTaskDef*def)
os << "class " << name << " : public vvm_thread {" << endl; os << "class " << name << " : public vvm_thread {" << endl;
os << " public:" << endl; os << " public:" << endl;
os << " " << name << "(vvm_simulation*sim, vvm_thread*th)" << endl; os << " " << name << "(vvm_thread*th)" << endl;
os << " : vvm_thread(sim), back_(th), step_(&" << name << "::step_0_)" << endl; os << " : vvm_thread(), back_(th), step_(&" << name << "::step_0_)" << endl;
os << " { }" << endl; os << " { }" << endl;
os << " ~" << name << "() { }" << endl; os << " ~" << name << "() { }" << endl;
os << " bool go() { return (this->*step_)(); }" << endl; os << " bool go() { return (this->*step_)(); }" << endl;
@ -813,7 +812,7 @@ void target_vvm::task_def(ostream&os, const NetTaskDef*def)
defn << "bool " << thread_class_ << "::step_0_() {" << endl; defn << "bool " << thread_class_ << "::step_0_() {" << endl;
def->proc()->emit_proc(os, this); def->proc()->emit_proc(os, this);
defn << " sim_->thread_active(back_);" << endl; defn << " back_ -> thread_yield();" << endl;
defn << " return false;" << endl; defn << " return false;" << endl;
defn << "}" << endl; defn << "}" << endl;
@ -834,10 +833,10 @@ void target_vvm::func_def(ostream&os, const NetFuncDef*def)
thread_step_ = 0; thread_step_ = 0;
const string name = mangle(def->name()); const string name = mangle(def->name());
os << "// Function " << def->name() << endl; os << "// Function " << def->name() << endl;
os << "static void " << name << "(vvm_simulation*);" << endl; os << "static void " << name << "();" << endl;
defn << "// Function " << def->name() << endl; defn << "// Function " << def->name() << endl;
defn << "static void " << name << "(vvm_simulation*sim_)" << endl; defn << "static void " << name << "()" << endl;
defn << "{" << endl; defn << "{" << endl;
def->proc()->emit_proc(os, this); def->proc()->emit_proc(os, this);
defn << "}" << endl; defn << "}" << endl;
@ -854,7 +853,7 @@ string target_vvm::defn_gate_outputfun_(ostream&os,
"_" << lnk.get_inst() << ends; "_" << lnk.get_inst() << ends;
string name = tmp.str(); string name = tmp.str();
os << "static void " << name << "(vvm_simulation*, vpip_bit_t);" << endl; os << "static void " << name << "(vpip_bit_t);" << endl;
return name; return name;
} }
@ -869,7 +868,7 @@ void target_vvm::emit_gate_outputfun_(const NetNode*gate, unsigned gpin)
delayed << "static void " << mangle(gate->name()) << delayed << "static void " << mangle(gate->name()) <<
"_output_" << lnk.get_name() << "_" << lnk.get_inst() << "_output_" << lnk.get_name() << "_" << lnk.get_inst() <<
"(vvm_simulation*sim, vpip_bit_t val)" << "(vpip_bit_t val)" <<
endl << "{" << endl; endl << "{" << endl;
/* The output function connects to gpin of the netlist part /* The output function connects to gpin of the netlist part
@ -884,12 +883,12 @@ void target_vvm::emit_gate_outputfun_(const NetNode*gate, unsigned gpin)
if (cur->pin(pin).get_name() != "") { if (cur->pin(pin).get_name() != "") {
delayed << " " << mangle(cur->name()) << ".set_" delayed << " " << mangle(cur->name()) << ".set_"
<< cur->pin(pin).get_name() << "(sim, " << << cur->pin(pin).get_name() << "(" <<
cur->pin(pin).get_inst() << ", val);" << endl; cur->pin(pin).get_inst() << ", val);" << endl;
} else { } else {
delayed << " " << mangle(cur->name()) << ".set(sim, " delayed << " " << mangle(cur->name()) << ".set("
<< pin << ", val);" << endl; << pin << ", val);" << endl;
} }
@ -1073,7 +1072,7 @@ void target_vvm::logic(ostream&os, const NetLogic*gate)
emit_gate_outputfun_(gate, 0); emit_gate_outputfun_(gate, 0);
start_code << " " << mangle(gate->name()) << start_code << " " << mangle(gate->name()) <<
".start(&sim);" << endl; ".start();" << endl;
} }
void target_vvm::bufz(ostream&os, const NetBUFZ*gate) void target_vvm::bufz(ostream&os, const NetBUFZ*gate)
@ -1174,18 +1173,17 @@ void target_vvm::net_assign_nb(ostream&os, const NetAssignNB*net)
os << " public:" << endl; os << " public:" << endl;
if (net->bmux()) { if (net->bmux()) {
os << " " << name << "(vvm_simulation*s, const vvm_bitset_t<" os << " " << name << "(const vvm_bitset_t<"
<< iwid << ">&v, unsigned idx)" << endl; << iwid << ">&v, unsigned idx)" << endl;
os << " : sim_(s), value_(v), idx_(idx) { }" << endl; os << " : value_(v), idx_(idx) { }" << endl;
} else { } else {
os << " " << name << "(vvm_simulation*s, const vvm_bits_t&v)" os << " " << name << "(const vvm_bits_t&v)"
<< endl; << endl;
os << " : sim_(s), value_(v) { }" << endl; os << " : value_(v) { }" << endl;
} }
os << " void event_function();" << endl; os << " void event_function();" << endl;
os << " private:" << endl; os << " private:" << endl;
os << " vvm_simulation*sim_;" << endl;
os << " vvm_bitset_t<" << iwid << ">value_;" << endl; os << " vvm_bitset_t<" << iwid << ">value_;" << endl;
if (net->bmux()) if (net->bmux())
@ -1220,7 +1218,7 @@ void target_vvm::net_assign_nb(ostream&os, const NetAssignNB*net)
continue; continue;
delayed << " " << mangle(cur->name()) delayed << " " << mangle(cur->name())
<< ".set_" << lnk.get_name() << "sim_, " << ".set_" << lnk.get_name()
<< lnk.get_inst() << ", value_[0]);" << endl; << lnk.get_inst() << ", value_[0]);" << endl;
} }
@ -1247,7 +1245,7 @@ void target_vvm::net_assign_nb(ostream&os, const NetAssignNB*net)
continue; continue;
delayed << " " << mangle(cur->name()) << delayed << " " << mangle(cur->name()) <<
".set_" << lnk.get_name() << "(sim_, " ".set_" << lnk.get_name() << "("
<< lnk.get_inst() << ", value_[" << << lnk.get_inst() << ", value_[" <<
idx << "]);" << endl; idx << "]);" << endl;
} }
@ -1262,7 +1260,7 @@ void target_vvm::net_case_cmp(ostream&os, const NetCaseCmp*gate)
os << "static void " << mangle(gate->name()) << os << "static void " << mangle(gate->name()) <<
"_output_" << lnk.get_name() << "_" << lnk.get_inst() << "_output_" << lnk.get_name() << "_" << lnk.get_inst() <<
"(vvm_simulation*, vpip_bit_t);" << endl; "(vpip_bit_t);" << endl;
assert(gate->pin_count() == 3); assert(gate->pin_count() == 3);
os << "static vvm_eeq" << "<" << gate->rise_time() << "> " os << "static vvm_eeq" << "<" << gate->rise_time() << "> "
@ -1271,8 +1269,7 @@ void target_vvm::net_case_cmp(ostream&os, const NetCaseCmp*gate)
emit_gate_outputfun_(gate, 0); emit_gate_outputfun_(gate, 0);
start_code << " " << mangle(gate->name()) << start_code << " " << mangle(gate->name()) << ".start();" << endl;
".start(&sim);" << endl;
} }
/* /*
@ -1288,7 +1285,7 @@ void target_vvm::net_const(ostream&os, const NetConst*gate)
os << "static vvm_bufz " << mangle(gate->name()) << "(&" << os << "static vvm_bufz " << mangle(gate->name()) << "(&" <<
outfun << ");" << endl; outfun << ");" << endl;
init_code << " " << mangle(gate->name()) << ".set(&sim, 1, "; init_code << " " << mangle(gate->name()) << ".set(1, ";
switch (gate->value()) { switch (gate->value()) {
case verinum::V0: case verinum::V0:
init_code << "V0"; init_code << "V0";
@ -1358,8 +1355,8 @@ void target_vvm::start_process(ostream&os, const NetProcTop*proc)
os << "class " << thread_class_ << " : public vvm_thread {" << endl; os << "class " << thread_class_ << " : public vvm_thread {" << endl;
os << " public:" << endl; os << " public:" << endl;
os << " " << thread_class_ << "(vvm_simulation*sim)" << endl; os << " " << thread_class_ << "()" << endl;
os << " : vvm_thread(sim), step_(&" << thread_class_ << os << " : vvm_thread(), step_(&" << thread_class_ <<
"::step_0_)" << endl; "::step_0_)" << endl;
os << " { }" << endl; os << " { }" << endl;
os << " ~" << thread_class_ << "() { }" << endl; os << " ~" << thread_class_ << "() { }" << endl;
@ -1417,7 +1414,7 @@ void target_vvm::proc_assign(ostream&os, const NetAssign*net)
written[cur->name()] = true; written[cur->name()] = true;
defn << " " << mangle(cur->name()) << defn << " " << mangle(cur->name()) <<
".set_" << cur->pin(pin).get_name() << ".set_" << cur->pin(pin).get_name() <<
"(sim_, " << cur->pin(pin).get_inst() << "(" << cur->pin(pin).get_inst() <<
", " << rval << "[0]);" << endl; ", " << rval << "[0]);" << endl;
} }
@ -1453,7 +1450,7 @@ void target_vvm::proc_assign(ostream&os, const NetAssign*net)
written[cur->name()] = true; written[cur->name()] = true;
defn << " " << mangle(cur->name()) << defn << " " << mangle(cur->name()) <<
".set_" << cur->pin(pin).get_name() << ".set_" << cur->pin(pin).get_name() <<
"(sim_, " << cur->pin(pin).get_inst() << "(" << cur->pin(pin).get_inst() <<
", " << rval << "[" << idx << "]);" << endl; ", " << rval << "[" << idx << "]);" << endl;
} }
} }
@ -1474,7 +1471,7 @@ void target_vvm::proc_assign_mem(ostream&os, const NetAssignMem*amem)
defn << " /* " << amem->get_line() << " */" << endl; defn << " /* " << amem->get_line() << " */" << endl;
if (mem->width() == amem->rval()->expr_width()) { if (mem->width() == amem->rval()->expr_width()) {
defn << " " << mangle(mem->name()) << defn << " " << mangle(mem->name()) <<
".set_word(sim_, " << index << ".as_unsigned(), " << ".set_word(" << index << ".as_unsigned(), " <<
rval << ");" << endl; rval << ");" << endl;
} else { } else {
@ -1486,7 +1483,7 @@ void target_vvm::proc_assign_mem(ostream&os, const NetAssignMem*amem)
defn << " " << tmp << "[" << idx << "] = " << defn << " " << tmp << "[" << idx << "] = " <<
rval << "[" << idx << "];" << endl; rval << "[" << idx << "];" << endl;
defn << " " << mangle(mem->name()) << ".set_word(sim_, " defn << " " << mangle(mem->name()) << ".set_word("
<< index << ".as_unsigned(), " << tmp << ");" << endl; << index << ".as_unsigned(), " << tmp << ");" << endl;
} }
} }
@ -1497,14 +1494,14 @@ void target_vvm::proc_assign_nb(ostream&os, const NetAssignNB*net)
if (net->bmux()) { if (net->bmux()) {
string bval = emit_proc_rval(defn, 8, net->bmux()); string bval = emit_proc_rval(defn, 8, net->bmux());
defn << " sim_->insert_event(" << net->rise_time() defn << " (new " << mangle(net->name()) << "("
<< ", new " << mangle(net->name()) << "(sim_, " << rval << rval << ", " << bval << ".as_unsigned())) "
<< ", " << bval << ".as_unsigned()));" << endl; << "-> schedule(" << net->rise_time() << ");" << endl;
} else { } else {
defn << " sim_->insert_event(" << net->rise_time() defn << " (new " << mangle(net->name()) << "("
<< ", new " << mangle(net->name()) << "(sim_, " << rval << rval << ")) -> schedule(" << net->rise_time() <<
<< "));" << endl; ");" << endl;
} }
} }
@ -1786,7 +1783,7 @@ void target_vvm::proc_utask(ostream&os, const NetUTask*net)
{ {
unsigned out_step = ++thread_step_; unsigned out_step = ++thread_step_;
const string name = mangle(net->name()); const string name = mangle(net->name());
defn << " callee_ = new " << name << "(sim_, this);" << endl; defn << " callee_ = new " << name << "(this);" << endl;
defn << " step_ = &" << thread_class_ << "::step_" << defn << " step_ = &" << thread_class_ << "::step_" <<
out_step << "_;" << endl; out_step << "_;" << endl;
defn << " return false;" << endl; defn << " return false;" << endl;
@ -1922,8 +1919,7 @@ void target_vvm::proc_delay(ostream&os, const NetPDelay*proc)
thread_step_ += 1; thread_step_ += 1;
defn << " step_ = &" << thread_class_ << "::step_" << defn << " step_ = &" << thread_class_ << "::step_" <<
thread_step_ << "_;" << endl; thread_step_ << "_;" << endl;
defn << " sim_->thread_delay(" << proc->delay() << ", this);" defn << " thread_yield(" << proc->delay() << ");" << endl;
<< endl;
defn << " return false;" << endl; defn << " return false;" << endl;
defn << "}" << endl; defn << "}" << endl;
@ -1959,6 +1955,9 @@ extern const struct target tgt_vvm = {
}; };
/* /*
* $Log: t-vvm.cc,v $ * $Log: t-vvm.cc,v $
* Revision 1.90 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.89 1999/12/12 06:03:14 steve * Revision 1.89 1999/12/12 06:03:14 steve
* Allow memories without indices in expressions. * Allow memories without indices in expressions.
* *
@ -2015,63 +2014,5 @@ extern const struct target tgt_vvm = {
* *
* Revision 1.72 1999/11/06 16:00:17 steve * Revision 1.72 1999/11/06 16:00:17 steve
* Put number constants into a static table. * Put number constants into a static table.
*
* Revision 1.71 1999/11/01 02:07:41 steve
* Add the synth functor to do generic synthesis
* and add the LPM_FF device to handle rows of
* flip-flops.
*
* Revision 1.70 1999/10/31 20:08:24 steve
* Include subtraction in LPM_ADD_SUB device.
*
* Revision 1.69 1999/10/31 04:11:28 steve
* Add to netlist links pin name and instance number,
* and arrange in vvm for pin connections by name
* and instance number.
*
* Revision 1.68 1999/10/28 21:51:21 steve
* gate output pins use vpip_bit_t (Eric Aardoom)
*
* Revision 1.67 1999/10/28 21:36:00 steve
* Get rid of monitor_t and fold __vpiSignal into signal.
*
* Revision 1.66 1999/10/28 04:48:29 steve
* Put strings into a single string table.
*
* Revision 1.65 1999/10/28 00:47:24 steve
* Rewrite vvm VPI support to make objects more
* persistent, rewrite the simulation scheduler
* in C (to interface with VPI) and add VPI support
* for callbacks.
*
* Revision 1.64 1999/10/23 16:27:53 steve
* assignment to bit select is aa single bit.
*
* Revision 1.63 1999/10/21 02:15:06 steve
* Make generated code ISO legal.
*
* Revision 1.62 1999/10/10 01:59:55 steve
* Structural case equals device.
*
* Revision 1.61 1999/10/08 02:00:48 steve
* vvm supports unary | operator.
*
* Revision 1.60 1999/10/07 05:25:34 steve
* Add non-const bit select in l-value of assignment.
*
* Revision 1.59 1999/10/06 01:28:18 steve
* The $finish task should work immediately.
*
* Revision 1.58 1999/10/05 06:19:46 steve
* Add support for reduction NOR.
*
* Revision 1.57 1999/10/05 04:02:10 steve
* Relaxed width handling for <= assignment.
*
* Revision 1.56 1999/10/01 15:26:28 steve
* Add some vvm operators from Eric Aardoom.
*
* Revision 1.55 1999/10/01 03:58:37 steve
* More resilient assignment to memory location.
*/ */

4
vvm/Makefile.in
View File

@ -18,7 +18,7 @@
# 59 Temple Place - Suite 330 # 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA # Boston, MA 02111-1307, USA
# #
#ident "$Id: Makefile.in,v 1.14 1999/11/27 19:07:58 steve Exp $" #ident "$Id: Makefile.in,v 1.15 1999/12/12 19:47:54 steve Exp $"
# #
# #
SHELL = /bin/sh SHELL = /bin/sh
@ -59,7 +59,7 @@ all: libvvm.a
mv $*.d dep mv $*.d dep
O = vvm_bit.o vvm_calltf.o vvm_event.o vvm_gates.o vvm_pevent.o \ O = vvm_bit.o vvm_calltf.o vvm_event.o vvm_gates.o vvm_pevent.o \
vvm_simulation.o vvm_thread.o vpip.o vvm_thread.o vpip.o
P = vpi_callback.o \ P = vpi_callback.o \
vpi_const.o vpi_iter.o vpi_memory.o vpi_null.o \ vpi_const.o vpi_iter.o vpi_memory.o vpi_null.o \

75
vvm/vvm.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm.h,v 1.26 1999/12/09 06:00:19 steve Exp $" #ident "$Id: vvm.h,v 1.27 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include <cassert> # include <cassert>
@ -33,8 +33,6 @@
typedef unsigned vvm_u32; typedef unsigned vvm_u32;
class vvm_event; class vvm_event;
class vvm_simulation;
class vvm_simulation_cycle;
class vvm_thread; class vvm_thread;
class ostream; class ostream;
@ -159,68 +157,24 @@ template <unsigned WIDTH> class vvm_bitset_t : public vvm_bits_t {
*/ */
class vvm_event { class vvm_event {
friend class vvm_simulation;
public: public:
vvm_event(); vvm_event();
virtual ~vvm_event() =0; virtual ~vvm_event() =0;
virtual void event_function() =0; virtual void event_function() =0;
static void callback_(void*); void schedule(unsigned long delay =0);
private: private:
struct vpip_event*event_; struct vpip_event*event_;
static void callback_(void*);
private: // not implemented private: // not implemented
vvm_event(const vvm_event&); vvm_event(const vvm_event&);
vvm_event& operator= (const vvm_event&); vvm_event& operator= (const vvm_event&);
}; };
/*
* This class is the main simulation engine. Object of this type are
* self-contained simulations. Generally, only one is needed.
*/
class vvm_simulation {
public:
vvm_simulation();
~vvm_simulation();
// Take a simulation that has been primed with some initial
// events, and run it. Continue running it until the
// simulation stops. The sim parameter becomes the new list,
// or 0 if the events run out. The simulation clock is
// advanced for the first cycle in sim.
void run();
// Add an event to an existing simulation cycle list. If there
// is not a cycle for the exact delay of the event, create one
// and insert it into the cycle list. Add the event to the
// list of events for the cycle time.
void insert_event(unsigned long delay, vvm_event*event);
// This puts the event in the current active list. No delay.
void active_event(vvm_event*event);
// These are versions of the *_event methods that take
// vvm_thread objects instead.
void thread_delay(unsigned long delay, vvm_thread*);
void thread_active(vvm_thread*);
// Trigger an event as a monitor event causes it to be
// scheduled and executed when the time cycle is
// complete. Unlike other events, the execution of a event so
// scheduled will not cause the event to be deleted. Also,
// only one event can be a monitor.
void monitor_event(vvm_event*);
bool finished() const;
private: // not implemented
vvm_simulation(const vvm_simulation&);
vvm_simulation& operator= (const vvm_simulation&);
};
/* /*
* The vvm_signal_t template is the real object that handles the * The vvm_signal_t template is the real object that handles the
@ -239,12 +193,12 @@ template <unsigned WIDTH> class vvm_signal_t : public __vpiSignal {
void init_P(unsigned idx, vpip_bit_t val) void init_P(unsigned idx, vpip_bit_t val)
{ bits[idx] = val; } { bits[idx] = val; }
void set_P(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_P(unsigned idx, vpip_bit_t val)
{ bits[idx] = val; { bits[idx] = val;
vpip_run_value_changes(this); vpip_run_value_changes(this);
} }
void set_P(vvm_simulation*sim, const vvm_bitset_t<WIDTH>&val) void set_P(const vvm_bitset_t<WIDTH>&val)
{ for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) { for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
set(sim, idx, val[idx]); set(sim, idx, val[idx]);
} }
@ -253,7 +207,7 @@ template <unsigned WIDTH> class vvm_signal_t : public __vpiSignal {
struct vvm_ram_callback { struct vvm_ram_callback {
vvm_ram_callback(); vvm_ram_callback();
virtual ~vvm_ram_callback(); virtual ~vvm_ram_callback();
virtual void handle_write(vvm_simulation*sim, unsigned idx) =0; virtual void handle_write(unsigned idx) =0;
vvm_ram_callback*next_; vvm_ram_callback*next_;
}; };
@ -265,20 +219,20 @@ class vvm_memory_t : public __vpiMemory {
{ cb_list_ = 0; { cb_list_ = 0;
} }
void set_word(vvm_simulation*sim, unsigned addr, void set_word(unsigned addr,
const vvm_bitset_t<WIDTH>&val) const vvm_bitset_t<WIDTH>&val)
{ unsigned base = WIDTH * addr; { unsigned base = WIDTH * addr;
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
bits[base+idx] = val[idx]; bits[base+idx] = val[idx];
call_list_(sim, addr); call_list_(addr);
} }
void set_word(vvm_simulation*sim, unsigned addr, void set_word(unsigned addr,
const vpip_bit_t val[WIDTH]) const vpip_bit_t val[WIDTH])
{ unsigned base = WIDTH * addr; { unsigned base = WIDTH * addr;
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
bits[base+idx] = val[idx]; bits[base+idx] = val[idx];
call_list_(sim, addr); call_list_(addr);
} }
vvm_bitset_t<WIDTH> get_word(unsigned addr) const vvm_bitset_t<WIDTH> get_word(unsigned addr) const
@ -296,14 +250,17 @@ class vvm_memory_t : public __vpiMemory {
private: private:
vvm_ram_callback*cb_list_; vvm_ram_callback*cb_list_;
void call_list_(vvm_simulation*sim, unsigned idx) void call_list_(unsigned idx)
{ for (vvm_ram_callback*cur = cb_list_; cur; cur = cur->next_) { for (vvm_ram_callback*cur = cb_list_; cur; cur = cur->next_)
cur->handle_write(sim, idx); cur->handle_write(idx);
} }
}; };
/* /*
* $Log: vvm.h,v $ * $Log: vvm.h,v $
* Revision 1.27 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.26 1999/12/09 06:00:19 steve * Revision 1.26 1999/12/09 06:00:19 steve
* Fix const/non-const errors. * Fix const/non-const errors.
* *

10
vvm/vvm_event.cc
View File

@ -17,7 +17,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_event.cc,v 1.2 1999/10/28 00:47:25 steve Exp $" #ident "$Id: vvm_event.cc,v 1.3 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -32,6 +32,11 @@ vvm_event::~vvm_event()
{ {
} }
void vvm_event::schedule(unsigned long delay)
{
event_ = vpip_sim_insert_event(delay, this, callback_, 0);
}
void vvm_event::callback_(void*cbd) void vvm_event::callback_(void*cbd)
{ {
vvm_event*obj = reinterpret_cast<vvm_event*>(cbd); vvm_event*obj = reinterpret_cast<vvm_event*>(cbd);
@ -41,6 +46,9 @@ void vvm_event::callback_(void*cbd)
/* /*
* $Log: vvm_event.cc,v $ * $Log: vvm_event.cc,v $
* Revision 1.3 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.2 1999/10/28 00:47:25 steve * Revision 1.2 1999/10/28 00:47:25 steve
* Rewrite vvm VPI support to make objects more * Rewrite vvm VPI support to make objects more
* persistent, rewrite the simulation scheduler * persistent, rewrite the simulation scheduler

20
vvm/vvm_gates.cc
View File

@ -23,13 +23,13 @@
* Picture Elements, Inc., 777 Panoramic Way, Berkeley, CA 94704. * Picture Elements, Inc., 777 Panoramic Way, Berkeley, CA 94704.
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_gates.cc,v 1.3 1999/12/02 04:54:11 steve Exp $" #ident "$Id: vvm_gates.cc,v 1.4 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include "vvm_gates.h" # include "vvm_gates.h"
vvm_out_event::vvm_out_event(vvm_simulation*s, vpip_bit_t v, action_t o) vvm_out_event::vvm_out_event(vpip_bit_t v, action_t o)
: output_(o), sim_(s), val_(v) : output_(o), val_(v)
{ {
} }
@ -39,7 +39,7 @@ vvm_out_event::~vvm_out_event()
void vvm_out_event::event_function() void vvm_out_event::event_function()
{ {
output_(sim_, val_); output_(val_);
} }
vvm_1bit_out::vvm_1bit_out(vvm_out_event::action_t o, unsigned d) vvm_1bit_out::vvm_1bit_out(vvm_out_event::action_t o, unsigned d)
@ -51,13 +51,10 @@ vvm_1bit_out::~vvm_1bit_out()
{ {
} }
void vvm_1bit_out::output(vvm_simulation*sim, vpip_bit_t val) void vvm_1bit_out::output(vpip_bit_t val)
{ {
vvm_event*ev = new vvm_out_event(sim, val, output_); vvm_event*ev = new vvm_out_event(val, output_);
if (delay_ > 0) ev -> schedule(delay_);
sim->insert_event(delay_, ev);
else
sim->active_event(ev);
} }
@ -146,6 +143,9 @@ void compute_mux(vpip_bit_t*out, unsigned wid,
/* /*
* $Log: vvm_gates.cc,v $ * $Log: vvm_gates.cc,v $
* Revision 1.4 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.3 1999/12/02 04:54:11 steve * Revision 1.3 1999/12/02 04:54:11 steve
* Handle mux sel of X, if inputs are equal. * Handle mux sel of X, if inputs are equal.
* *

238
vvm/vvm_gates.h
View File

@ -1,7 +1,7 @@
#ifndef __vvm_gates_H #ifndef __vvm_gates_H
#define __vvm_gates_H #define __vvm_gates_H
/* /*
* Copyright (c) 1998 Stephen Williams (steve@icarus.com) * Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
* *
* This source code is free software; you can redistribute it * This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU * and/or modify it in source code form under the terms of the GNU
@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_gates.h,v 1.31 1999/12/05 02:24:09 steve Exp $" #ident "$Id: vvm_gates.h,v 1.32 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -47,16 +47,15 @@ extern void compute_mux(vpip_bit_t*out, unsigned wid,
class vvm_out_event : public vvm_event { class vvm_out_event : public vvm_event {
public: public:
typedef void (*action_t)(vvm_simulation*, vpip_bit_t); typedef void (*action_t)(vpip_bit_t);
vvm_out_event(vvm_simulation*s, vpip_bit_t v, action_t o); vvm_out_event(vpip_bit_t v, action_t o);
~vvm_out_event(); ~vvm_out_event();
void event_function(); void event_function();
private: private:
const action_t output_; const action_t output_;
vvm_simulation*const sim_;
const vpip_bit_t val_; const vpip_bit_t val_;
}; };
@ -65,7 +64,7 @@ class vvm_1bit_out {
public: public:
vvm_1bit_out(vvm_out_event::action_t, unsigned delay); vvm_1bit_out(vvm_out_event::action_t, unsigned delay);
~vvm_1bit_out(); ~vvm_1bit_out();
void output(vvm_simulation*sim, vpip_bit_t); void output(vpip_bit_t);
private: private:
vvm_out_event::action_t output_; vvm_out_event::action_t output_;
@ -100,13 +99,13 @@ template <unsigned WIDTH> class vvm_add_sub {
{ ndir_ = not(val); { ndir_ = not(val);
} }
void set_DataA(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_DataA(unsigned idx, vpip_bit_t val)
{ a_[idx] = val; { a_[idx] = val;
compute_(sim); compute_();
} }
void set_DataB(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_DataB(unsigned idx, vpip_bit_t val)
{ b_[idx] = val; { b_[idx] = val;
compute_(sim); compute_();
} }
private: private:
@ -120,7 +119,7 @@ template <unsigned WIDTH> class vvm_add_sub {
vvm_out_event::action_t o_[WIDTH]; vvm_out_event::action_t o_[WIDTH];
void compute_(vvm_simulation*sim) void compute_()
{ vpip_bit_t carry = ndir_; { vpip_bit_t carry = ndir_;
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) { for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) {
vpip_bit_t val; vpip_bit_t val;
@ -128,8 +127,8 @@ template <unsigned WIDTH> class vvm_add_sub {
if (val == r_[idx]) continue; if (val == r_[idx]) continue;
r_[idx] = val; r_[idx] = val;
if (o_[idx] == 0) continue; if (o_[idx] == 0) continue;
vvm_event*ev = new vvm_out_event(sim, val, o_[idx]); vvm_event*ev = new vvm_out_event(val, o_[idx]);
sim->insert_event(0, ev); ev->schedule();
} }
} }
}; };
@ -144,13 +143,13 @@ class vvm_and : private vvm_1bit_out {
void init_I(unsigned idx, vpip_bit_t val) void init_I(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ output(sim, compute_and(input_,WIDTH)); } { output(compute_and(input_,WIDTH)); }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) return; { if (input_[idx] == val) return;
input_[idx] = val; input_[idx] = val;
output(sim, compute_and(input_,WIDTH)); output(compute_and(input_,WIDTH));
} }
private: private:
@ -183,29 +182,29 @@ template <unsigned WIDTH, unsigned WDIST> class vvm_clshift {
void init_Direction(vpip_bit_t val) void init_Direction(vpip_bit_t val)
{ dir_ = val; } { dir_ = val; }
void set_Data(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_Data(unsigned idx, vpip_bit_t val)
{ if (data_[idx] == val) return; { if (data_[idx] == val) return;
data_[idx] = val; data_[idx] = val;
if ((dist_val_ + idx) >= WIDTH) return; if ((dist_val_ + idx) >= WIDTH) return;
if ((dist_val_ + idx) < 0) return; if ((dist_val_ + idx) < 0) return;
vvm_out_event::action_t out = out_[dist_val_+idx]; vvm_out_event::action_t out = out_[dist_val_+idx];
if (out == 0) return; if (out == 0) return;
vvm_event*ev = new vvm_out_event(sim, val, out); vvm_event*ev = new vvm_out_event(val, out);
sim->active_event(ev); ev->schedule();
} }
void set_Distance(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_Distance(unsigned idx, vpip_bit_t val)
{ if (dist_[idx] == val) return; { if (dist_[idx] == val) return;
dist_[idx] = val; dist_[idx] = val;
calculate_dist_(); calculate_dist_();
compute_(sim); compute_();
} }
void set_Direction(vvm_simulation*sim, unsigned, vpip_bit_t val) void set_Direction(unsigned, vpip_bit_t val)
{ if (dir_ == val) return; { if (dir_ == val) return;
dir_ = val; dir_ = val;
calculate_dist_(); calculate_dist_();
compute_(sim); compute_();
} }
void config_rout(unsigned idx, vvm_out_event::action_t o) void config_rout(unsigned idx, vvm_out_event::action_t o)
@ -238,13 +237,13 @@ template <unsigned WIDTH, unsigned WDIST> class vvm_clshift {
dist_val_ = tmp; dist_val_ = tmp;
} }
void compute_(vvm_simulation*sim) void compute_()
{ vvm_event*ev; { vvm_event*ev;
if (dist_val_ == WIDTH) { if (dist_val_ == WIDTH) {
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) { for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) {
if (out_[idx] == 0) continue; if (out_[idx] == 0) continue;
ev = new vvm_out_event(sim, Vx, out_[idx]); ev = new vvm_out_event(Vx, out_[idx]);
sim->active_event(ev); ev->schedule();
} }
return; return;
} }
@ -254,8 +253,8 @@ template <unsigned WIDTH, unsigned WDIST> class vvm_clshift {
if ((idx-dist_val_) >= WIDTH) val = V0; if ((idx-dist_val_) >= WIDTH) val = V0;
else if ((idx-dist_val_) < 0) val = V0; else if ((idx-dist_val_) < 0) val = V0;
else val = data_[idx-dist_val_]; else val = data_[idx-dist_val_];
ev = new vvm_out_event(sim, val, out_[idx]); ev = new vvm_out_event(val, out_[idx]);
sim->active_event(ev); ev->schedule();
} }
} }
}; };
@ -280,16 +279,16 @@ template <unsigned WIDTH> class vvm_compare {
void init_DataB(unsigned idx, vpip_bit_t val) void init_DataB(unsigned idx, vpip_bit_t val)
{ b_[idx] = val; } { b_[idx] = val; }
void set_DataA(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_DataA(unsigned idx, vpip_bit_t val)
{ if (a_[idx] == val) return; { if (a_[idx] == val) return;
a_[idx] = val; a_[idx] = val;
compute_(sim); compute_();
} }
void set_DataB(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_DataB(unsigned idx, vpip_bit_t val)
{ if (b_[idx] == val) return; { if (b_[idx] == val) return;
b_[idx] = val; b_[idx] = val;
compute_(sim); compute_();
} }
void config_ALB_out(vvm_out_event::action_t o) void config_ALB_out(vvm_out_event::action_t o)
@ -316,7 +315,7 @@ template <unsigned WIDTH> class vvm_compare {
vvm_out_event::action_t out_gt_; vvm_out_event::action_t out_gt_;
vvm_out_event::action_t out_ge_; vvm_out_event::action_t out_ge_;
void compute_(vvm_simulation*sim) void compute_()
{ vpip_bit_t gt = V0; { vpip_bit_t gt = V0;
vpip_bit_t lt = V0; vpip_bit_t lt = V0;
vvm_event*ev; vvm_event*ev;
@ -329,20 +328,20 @@ template <unsigned WIDTH> class vvm_compare {
gt_ = gt; gt_ = gt;
lt_ = lt; lt_ = lt;
if (out_lt_) { if (out_lt_) {
ev = new vvm_out_event(sim, lt_, out_lt_); ev = new vvm_out_event(lt_, out_lt_);
sim->active_event(ev); ev->schedule();
} }
if (out_le_) { if (out_le_) {
ev = new vvm_out_event(sim, not(gt_), out_le_); ev = new vvm_out_event(not(gt_), out_le_);
sim->active_event(ev); ev->schedule();
} }
if (out_gt_) { if (out_gt_) {
ev = new vvm_out_event(sim, gt_, out_gt_); ev = new vvm_out_event(gt_, out_gt_);
sim->active_event(ev); ev->schedule();
} }
if (out_ge_) { if (out_ge_) {
ev = new vvm_out_event(sim, not(lt_), out_ge_); ev = new vvm_out_event(not(lt_), out_ge_);
sim->active_event(ev); ev->schedule();
} }
} }
}; };
@ -365,14 +364,14 @@ template <unsigned WIDTH> class vvm_ff {
void init_Data(unsigned idx, vpip_bit_t val) { d_[idx] = val; } void init_Data(unsigned idx, vpip_bit_t val) { d_[idx] = val; }
void init_Clock(unsigned, vpip_bit_t val) { clk_ = val; } void init_Clock(unsigned, vpip_bit_t val) { clk_ = val; }
void set_Clock(vvm_simulation*sim, unsigned, vpip_bit_t val) void set_Clock(unsigned, vpip_bit_t val)
{ if (val == clk_) return; { if (val == clk_) return;
bool flag = posedge(clk_, val); bool flag = posedge(clk_, val);
clk_ = val; clk_ = val;
if (flag) latch_(sim); if (flag) latch_();
} }
void set_Data(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_Data(unsigned idx, vpip_bit_t val)
{ d_[idx] = val; { d_[idx] = val;
} }
@ -387,13 +386,12 @@ template <unsigned WIDTH> class vvm_ff {
vvm_out_event::action_t out_[WIDTH]; vvm_out_event::action_t out_[WIDTH];
void latch_(vvm_simulation*sim) void latch_()
{ q_ = d_; { q_ = d_;
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
if (out_[idx]) { if (out_[idx]) {
vvm_event*ev = new vvm_out_event(sim, q_[idx], vvm_event*ev = new vvm_out_event(q_[idx], out_[idx]);
out_[idx]); ev->schedule();
sim->active_event(ev);
} }
} }
}; };
@ -420,16 +418,16 @@ template <unsigned WIDTH, unsigned SIZE, unsigned SELWID> class vvm_mux {
void init_Data(unsigned idx, vpip_bit_t val) void init_Data(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void set_Sel(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_Sel(unsigned idx, vpip_bit_t val)
{ if (sel_[idx] == val) return; { if (sel_[idx] == val) return;
sel_[idx] = val; sel_[idx] = val;
evaluate_(sim); evaluate_();
} }
void set_Data(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_Data(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) return; { if (input_[idx] == val) return;
input_[idx] = val; input_[idx] = val;
evaluate_(sim); evaluate_();
} }
void config_rout(unsigned idx, vvm_out_event::action_t o) void config_rout(unsigned idx, vvm_out_event::action_t o)
@ -442,16 +440,15 @@ template <unsigned WIDTH, unsigned SIZE, unsigned SELWID> class vvm_mux {
vvm_out_event::action_t out_[WIDTH]; vvm_out_event::action_t out_[WIDTH];
void evaluate_(vvm_simulation*sim) void evaluate_()
{ vpip_bit_t tmp[WIDTH]; { vpip_bit_t tmp[WIDTH];
compute_mux(tmp, WIDTH, sel_, SELWID, input_, SIZE); compute_mux(tmp, WIDTH, sel_, SELWID, input_, SIZE);
for (unsigned idx = 0 ; idx < WIDTH ; idx += 1) for (unsigned idx = 0 ; idx < WIDTH ; idx += 1)
if (tmp[idx] != output_[idx]) { if (tmp[idx] != output_[idx]) {
output_[idx] = tmp[idx]; output_[idx] = tmp[idx];
vvm_event*ev = new vvm_out_event(sim, vvm_event*ev = new vvm_out_event(output_[idx],
output_[idx],
out_[idx]); out_[idx]);
sim->active_event(ev); ev->schedule();
} }
} }
}; };
@ -466,14 +463,14 @@ class vvm_or : private vvm_1bit_out {
void init_I(unsigned idx, vpip_bit_t val) void init_I(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ output(sim, compute_or(input_,WIDTH)); } { output(compute_or(input_,WIDTH)); }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) { if (input_[idx] == val)
return; return;
input_[idx] = val; input_[idx] = val;
output(sim, compute_or(input_,WIDTH)); output(compute_or(input_,WIDTH));
} }
private: private:
@ -490,14 +487,14 @@ class vvm_nor : private vvm_1bit_out {
void init_I(unsigned idx, vpip_bit_t val) void init_I(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ output(sim, compute_nor(input_,WIDTH)); } { output(compute_nor(input_,WIDTH)); }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) { if (input_[idx] == val)
return; return;
input_[idx] = val; input_[idx] = val;
output(sim, compute_nor(input_,WIDTH)); output(compute_nor(input_,WIDTH));
} }
private: private:
@ -538,29 +535,29 @@ class vvm_ram_dq : protected vvm_ram_callback {
void init_InClock(unsigned, vpip_bit_t val) void init_InClock(unsigned, vpip_bit_t val)
{ iclk_ = val; } { iclk_ = val; }
void set_Address(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_Address(unsigned idx, vpip_bit_t val)
{ if (addr_[idx] == val) return; { if (addr_[idx] == val) return;
addr_[idx] = val; addr_[idx] = val;
compute_(); compute_();
send_out_(sim); send_out_();
} }
void set_Data(vvm_simulation*, unsigned idx, vpip_bit_t val) void set_Data(unsigned idx, vpip_bit_t val)
{ data_[idx] = val; } { data_[idx] = val; }
void set_WE(vvm_simulation*, unsigned, vpip_bit_t val) void set_WE(unsigned, vpip_bit_t val)
{ we_ = val; } { we_ = val; }
void set_InClock(vvm_simulation*sim, unsigned, vpip_bit_t val) void set_InClock(unsigned, vpip_bit_t val)
{ if (val == iclk_) return; { if (val == iclk_) return;
vpip_bit_t tmp = iclk_; vpip_bit_t tmp = iclk_;
iclk_ = val; iclk_ = val;
if (we_ != V1) return; if (we_ != V1) return;
if (posedge(tmp, val)) mem_->set_word(sim, addr_val_, data_); if (posedge(tmp, val)) mem_->set_word(addr_val_, data_);
} }
void handle_write(vvm_simulation*sim, unsigned idx) void handle_write(unsigned idx)
{ if (idx == addr_val_) send_out_(sim); } { if (idx == addr_val_) send_out_(); }
void config_rout(unsigned idx, vvm_out_event::action_t o) void config_rout(unsigned idx, vvm_out_event::action_t o)
{ out_[idx] = o; } { out_[idx] = o; }
@ -585,14 +582,13 @@ class vvm_ram_dq : protected vvm_ram_callback {
if (addr_[bit] == V1) addr_val_ |= mask; if (addr_[bit] == V1) addr_val_ |= mask;
} }
void send_out_(vvm_simulation*sim) void send_out_()
{ vvm_bitset_t<WIDTH>ov = mem_->get_word(addr_val_); { vvm_bitset_t<WIDTH>ov = mem_->get_word(addr_val_);
for (unsigned bit = 0 ; bit < WIDTH ; bit += 1) for (unsigned bit = 0 ; bit < WIDTH ; bit += 1)
if (out_[bit]) { if (out_[bit]) {
vvm_event*ev = new vvm_out_event(sim, vvm_event*ev = new vvm_out_event(ov[bit],
ov[bit],
out_[bit]); out_[bit]);
sim->active_event(ev); ev->schedule();
} }
} }
}; };
@ -605,16 +601,13 @@ template <unsigned long DELAY> class vvm_buf {
{ } { }
void init_I(unsigned, vpip_bit_t) { } void init_I(unsigned, vpip_bit_t) { }
void start(vvm_simulation*) { } void start() { }
void set_I(vvm_simulation*sim, unsigned, vpip_bit_t val) void set_I(unsigned, vpip_bit_t val)
{ vpip_bit_t outval = val; { vpip_bit_t outval = val;
if (val == Vz) val = Vx; if (val == Vz) val = Vx;
vvm_event*ev = new vvm_out_event(sim, outval, output_); vvm_event*ev = new vvm_out_event(outval, output_);
if (DELAY > 0) ev->schedule(DELAY);
sim->insert_event(DELAY, ev);
else
sim->active_event(ev);
} }
private: private:
@ -630,18 +623,15 @@ template <unsigned long DELAY> class vvm_bufif1 {
input_[1] = Vx; input_[1] = Vx;
} }
void set(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set(unsigned idx, vpip_bit_t val)
{ if (input_[idx-1] == val) { if (input_[idx-1] == val)
return; return;
input_[idx-1] = val; input_[idx-1] = val;
vvm_event*ev = new vvm_out_event(sim, compute_(), output_); vvm_event*ev = new vvm_out_event(compute_(), output_);
if (DELAY > 0) ev->schedule(DELAY);
sim->insert_event(DELAY, ev);
else
sim->active_event(ev);
} }
void start(vvm_simulation*sim) void start()
{ {
} }
@ -666,13 +656,13 @@ class vvm_nand : private vvm_1bit_out {
void init_I(unsigned idx, vpip_bit_t val) void init_I(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ output(sim, compute_nand(input_,WIDTH)); } { output(compute_nand(input_,WIDTH)); }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) return; { if (input_[idx] == val) return;
input_[idx] = val; input_[idx] = val;
output(sim, compute_nand(input_,WIDTH)); output(compute_nand(input_,WIDTH));
} }
private: private:
@ -689,10 +679,10 @@ template <unsigned long DELAY> class vvm_not : private vvm_1bit_out {
: vvm_1bit_out(o, DELAY) { } : vvm_1bit_out(o, DELAY) { }
void init_I(unsigned, vpip_bit_t) { } void init_I(unsigned, vpip_bit_t) { }
void start(vvm_simulation*) { } void start() { }
void set_I(vvm_simulation*sim, unsigned, vpip_bit_t val) void set_I(unsigned, vpip_bit_t val)
{ output(sim, not(val)); } { output(not(val)); }
private: private:
}; };
@ -706,14 +696,14 @@ class vvm_xnor : private vvm_1bit_out {
void init_I(unsigned idx, vpip_bit_t val) { input_[idx] = val; } void init_I(unsigned idx, vpip_bit_t val) { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ output(sim,compute_xnor(input_,WIDTH)); } { output(compute_xnor(input_,WIDTH)); }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) { if (input_[idx] == val)
return; return;
input_[idx] = val; input_[idx] = val;
output(sim,compute_xnor(input_,WIDTH)); output(compute_xnor(input_,WIDTH));
} }
private: private:
@ -730,14 +720,14 @@ class vvm_xor : private vvm_1bit_out {
void init_I(unsigned idx, vpip_bit_t val) void init_I(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ output(sim,compute_xor(input_,WIDTH)); } { output(compute_xor(input_,WIDTH)); }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) { if (input_[idx] == val)
return; return;
input_[idx] = val; input_[idx] = val;
output(sim,compute_xor(input_,WIDTH)); } output(compute_xor(input_,WIDTH)); }
private: private:
vpip_bit_t input_[WIDTH]; vpip_bit_t input_[WIDTH];
@ -756,19 +746,16 @@ template <unsigned long DELAY> class vvm_eeq {
void init_I(unsigned idx, vpip_bit_t val) void init_I(unsigned idx, vpip_bit_t val)
{ input_[idx] = val; } { input_[idx] = val; }
void start(vvm_simulation*sim) void start()
{ vvm_event*ev = new vvm_out_event(sim, compute_(), output_); { vvm_event*ev = new vvm_out_event(compute_(), output_);
if (DELAY > 0) ev->schedule(DELAY);
sim->insert_event(DELAY, ev);
else
sim->active_event(ev);
} }
void set_I(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_I(unsigned idx, vpip_bit_t val)
{ if (input_[idx] == val) { if (input_[idx] == val)
return; return;
input_[idx] = val; input_[idx] = val;
start(sim); start();
} }
private: private:
@ -805,7 +792,7 @@ template <unsigned WIDTH> class vvm_udp_ssequ {
void init(unsigned pin, vpip_bit_t val) void init(unsigned pin, vpip_bit_t val)
{ state_[pin] = val; } { state_[pin] = val; }
void set(vvm_simulation*sim, unsigned pin, vpip_bit_t val) void set(unsigned pin, vpip_bit_t val)
{ assert(pin > 0); { assert(pin > 0);
assert(pin < WIDTH+1); assert(pin < WIDTH+1);
if (val == Vz) val = Vx; if (val == Vz) val = Vx;
@ -836,8 +823,8 @@ template <unsigned WIDTH> class vvm_udp_ssequ {
vpip_bit_t outval = (code == 0)? V0 : (code == 1)? V1 : Vx; vpip_bit_t outval = (code == 0)? V0 : (code == 1)? V1 : Vx;
state_[0] = outval; state_[0] = outval;
state_[pin] = val; state_[pin] = val;
vvm_event*ev = new vvm_out_event(sim, outval, output_); vvm_event*ev = new vvm_out_event(outval, output_);
sim->insert_event(1, ev); // XXXX Delay not supported. ev->schedule(1); // XXXX Delay not supported.
} }
private: private:
@ -854,8 +841,8 @@ class vvm_bufz {
void init(unsigned idx, vpip_bit_t val) { } void init(unsigned idx, vpip_bit_t val) { }
void set(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set(unsigned idx, vpip_bit_t val)
{ output_(sim, val); } { output_(val); }
private: private:
vvm_out_event::action_t output_; vvm_out_event::action_t output_;
@ -877,7 +864,7 @@ class vvm_sync {
vvm_sync(); vvm_sync();
void wait(vvm_thread*); void wait(vvm_thread*);
void wakeup(vvm_simulation*sim); void wakeup();
private: private:
vvm_thread*hold_; vvm_thread*hold_;
@ -899,19 +886,19 @@ template <unsigned WIDTH> class vvm_pevent {
vvm_bitset_t<WIDTH> get() const { return value_; } vvm_bitset_t<WIDTH> get() const { return value_; }
void set_P(vvm_simulation*sim, unsigned idx, vpip_bit_t val) void set_P(unsigned idx, vpip_bit_t val)
{ if (value_[idx] == val) return; { if (value_[idx] == val) return;
switch (edge_) { switch (edge_) {
case ANYEDGE: case ANYEDGE:
target_->wakeup(sim); target_->wakeup();
break; break;
case POSEDGE: case POSEDGE:
if (val == V1) if (val == V1)
target_->wakeup(sim); target_->wakeup();
break; break;
case NEGEDGE: case NEGEDGE:
if (val == V0) if (val == V0)
target_->wakeup(sim); target_->wakeup();
break; break;
} }
value_[idx] = val; value_[idx] = val;
@ -934,6 +921,9 @@ template <unsigned WIDTH> class vvm_pevent {
/* /*
* $Log: vvm_gates.h,v $ * $Log: vvm_gates.h,v $
* Revision 1.32 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.31 1999/12/05 02:24:09 steve * Revision 1.31 1999/12/05 02:24:09 steve
* Synthesize LPM_RAM_DQ for writes into memories. * Synthesize LPM_RAM_DQ for writes into memories.
* *

10
vvm/vvm_pevent.cc
View File

@ -17,11 +17,12 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_pevent.cc,v 1.3 1999/05/01 20:43:55 steve Exp $" #ident "$Id: vvm_pevent.cc,v 1.4 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
# include "vvm_gates.h" # include "vvm_gates.h"
# include "vvm_thread.h"
vvm_sync::vvm_sync() vvm_sync::vvm_sync()
: hold_(0) : hold_(0)
@ -34,16 +35,19 @@ void vvm_sync::wait(vvm_thread*thr)
hold_ = thr; hold_ = thr;
} }
void vvm_sync::wakeup(vvm_simulation*sim) void vvm_sync::wakeup()
{ {
vvm_thread*tmp = hold_; vvm_thread*tmp = hold_;
hold_ = 0; hold_ = 0;
if (tmp) sim->thread_active(tmp); if (tmp) tmp->thread_yield();
} }
/* /*
* $Log: vvm_pevent.cc,v $ * $Log: vvm_pevent.cc,v $
* Revision 1.4 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.3 1999/05/01 20:43:55 steve * Revision 1.3 1999/05/01 20:43:55 steve
* Handle wide events, such as @(a) where a has * Handle wide events, such as @(a) where a has
* many bits in it. * many bits in it.

115
vvm/vvm_simulation.cc
View File

@ -1,115 +0,0 @@
/*
* Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#if !defined(WINNT)
#ident "$Id: vvm_simulation.cc,v 1.7 1999/10/28 00:47:25 steve Exp $"
#endif
# include "vvm.h"
# include "vvm_thread.h"
# include "vpi_priv.h"
# include <assert.h>
vvm_simulation::vvm_simulation()
{
}
vvm_simulation::~vvm_simulation()
{
}
void vvm_simulation::monitor_event(vvm_event*)
{
assert(0);
}
void vvm_simulation::insert_event(unsigned long delay, vvm_event*event)
{
event->event_ = vpip_sim_insert_event(delay, event,
vvm_event::callback_, 0);
}
void vvm_simulation::active_event(vvm_event*event)
{
event->event_ = vpip_sim_insert_event(0, event,
vvm_event::callback_, 0);
}
/*
* This function takes a list of simulation cycles and runs the
* simulation. It consumes the list as the events are executes,
* eventually deleting everything.
*/
void vvm_simulation::run()
{
vpip_simulation_run();
}
class delay_event : public vvm_event {
public:
delay_event(vvm_thread*thr) : thr_(thr) { }
void event_function() { while (thr_->go()) /* empty */; }
private:
vvm_thread*thr_;
};
void vvm_simulation::thread_delay(unsigned long delay, vvm_thread*thr)
{
delay_event*ev = new delay_event(thr);
insert_event(delay, ev);
}
void vvm_simulation::thread_active(vvm_thread*thr)
{
delay_event*ev = new delay_event(thr);
active_event(ev);
}
/*
* $Log: vvm_simulation.cc,v $
* Revision 1.7 1999/10/28 00:47:25 steve
* Rewrite vvm VPI support to make objects more
* persistent, rewrite the simulation scheduler
* in C (to interface with VPI) and add VPI support
* for callbacks.
*
* Revision 1.6 1999/10/06 01:28:18 steve
* The $finish task should work immediately.
*
* Revision 1.5 1999/09/29 02:53:33 steve
* Useless assertion.
*
* Revision 1.4 1999/06/19 03:31:33 steve
* End run if events run out.
*
* Revision 1.3 1999/06/07 03:40:03 steve
* Allow 0 delays for things like thread yield.
*
* Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait).
* Fix display of $time is format strings.
*
* Revision 1.1 1998/11/09 23:44:11 steve
* Add vvm library.
*
*/

26
vvm/vvm_thread.cc
View File

@ -17,24 +17,42 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_thread.cc,v 1.1 1998/11/09 23:44:11 steve Exp $" #ident "$Id: vvm_thread.cc,v 1.2 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
# include "vvm_thread.h" # include "vvm_thread.h"
vvm_thread::vvm_thread(vvm_simulation*sim)
: sim_(sim) class delay_event : public vvm_event {
public:
delay_event(vvm_thread*thr) : thr_(thr) { }
void event_function() { while (thr_->go()) /* empty */; }
private:
vvm_thread*thr_;
};
vvm_thread::vvm_thread()
{ {
sim_->thread_active(this); thread_yield();
} }
vvm_thread::~vvm_thread() vvm_thread::~vvm_thread()
{ {
} }
void vvm_thread::thread_yield(unsigned long delay)
{
delay_event*ev = new delay_event(this);
ev -> schedule(delay);
}
/* /*
* $Log: vvm_thread.cc,v $ * $Log: vvm_thread.cc,v $
* Revision 1.2 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.1 1998/11/09 23:44:11 steve * Revision 1.1 1998/11/09 23:44:11 steve
* Add vvm library. * Add vvm library.
* *

10
vvm/vvm_thread.h
View File

@ -19,7 +19,7 @@
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/ */
#if !defined(WINNT) #if !defined(WINNT)
#ident "$Id: vvm_thread.h,v 1.2 1998/11/10 00:48:31 steve Exp $" #ident "$Id: vvm_thread.h,v 1.3 1999/12/12 19:47:54 steve Exp $"
#endif #endif
# include "vvm.h" # include "vvm.h"
@ -36,20 +36,24 @@
class vvm_thread { class vvm_thread {
public: public:
explicit vvm_thread(vvm_simulation*sim); explicit vvm_thread();
virtual ~vvm_thread(); virtual ~vvm_thread();
void thread_yield(unsigned long delay =0);
// This method executes a setp of the thread. The engine will // This method executes a setp of the thread. The engine will
// continue to call go as long as it returns true. The thread // continue to call go as long as it returns true. The thread
// will return false if it is ready to give up the CPU. // will return false if it is ready to give up the CPU.
virtual bool go() =0; virtual bool go() =0;
protected: protected:
vvm_simulation*const sim_;
}; };
/* /*
* $Log: vvm_thread.h,v $ * $Log: vvm_thread.h,v $
* Revision 1.3 1999/12/12 19:47:54 steve
* Remove the useless vvm_simulation class.
*
* Revision 1.2 1998/11/10 00:48:31 steve * Revision 1.2 1998/11/10 00:48:31 steve
* Add support it vvm target for level-sensitive * Add support it vvm target for level-sensitive
* triggers (i.e. the Verilog wait). * triggers (i.e. the Verilog wait).