Fix for br974 - support SV types in non-ansi port declarations.
This commit is contained in:
Martin Whitaker
parent
9f88b26a67
commit
6ba2bee977
161
parse.y
161
parse.y
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@ -135,17 +135,17 @@ static list<named_pexpr_t>*attributes_in_context = 0;
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static const struct str_pair_t pull_strength = { IVL_DR_PULL, IVL_DR_PULL };
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static const struct str_pair_t str_strength = { IVL_DR_STRONG, IVL_DR_STRONG };
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static list<pair<perm_string,PExpr*> >* make_port_list(char*id, PExpr*expr)
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static list<pform_port_t>* make_port_list(char*id, list<pform_range_t>*udims, PExpr*expr)
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{
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list<pair<perm_string,PExpr*> >*tmp = new list<pair<perm_string,PExpr*> >;
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tmp->push_back(make_pair(lex_strings.make(id), expr));
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list<pform_port_t>*tmp = new list<pform_port_t>;
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tmp->push_back(pform_port_t(lex_strings.make(id), udims, expr));
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delete[]id;
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return tmp;
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}
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static list<pair<perm_string,PExpr*> >* make_port_list(list<pair<perm_string, PExpr*> >*tmp,
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char*id, PExpr*expr)
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static list<pform_port_t>* make_port_list(list<pform_port_t>*tmp,
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char*id, list<pform_range_t>*udims, PExpr*expr)
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{
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tmp->push_back(make_pair(lex_strings.make(id), expr));
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tmp->push_back(pform_port_t(lex_strings.make(id), udims, expr));
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delete[]id;
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return tmp;
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}
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@ -374,7 +374,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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char*text;
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list<perm_string>*perm_strings;
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list<pair<perm_string,PExpr*> >*port_list;
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list<pform_port_t>*port_list;
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vector<pform_tf_port_t>* tf_ports;
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@ -582,7 +582,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%type <text> register_variable net_variable event_variable endlabel_opt class_declaration_endlabel_opt
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%type <perm_strings> register_variable_list net_variable_list event_variable_list
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%type <perm_strings> list_of_identifiers loop_variables
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%type <port_list> list_of_port_identifiers
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%type <port_list> list_of_port_identifiers list_of_variable_port_identifiers
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%type <net_decl_assign> net_decl_assign net_decl_assigns
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@ -642,7 +642,7 @@ static void current_function_set_statement(const YYLTYPE&loc, vector<Statement*>
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%type <ranges> variable_dimension
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%type <ranges> dimensions_opt dimensions
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%type <nettype> net_type var_type net_type_opt
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%type <nettype> net_type net_type_opt
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%type <gatetype> gatetype switchtype
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%type <porttype> port_direction port_direction_opt
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%type <vartype> bit_logic bit_logic_opt
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@ -4057,14 +4057,21 @@ list_of_identifiers
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;
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list_of_port_identifiers
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: IDENTIFIER
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{ $$ = make_port_list($1, 0); }
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| IDENTIFIER '=' expression
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{ $$ = make_port_list($1, $3); }
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| list_of_port_identifiers ',' IDENTIFIER
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{ $$ = make_port_list($1, $3, 0); }
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| list_of_port_identifiers ',' IDENTIFIER '=' expression
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{ $$ = make_port_list($1, $3, $5); }
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: IDENTIFIER dimensions_opt
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{ $$ = make_port_list($1, $2, 0); }
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| list_of_port_identifiers ',' IDENTIFIER dimensions_opt
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{ $$ = make_port_list($1, $3, $4, 0); }
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;
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list_of_variable_port_identifiers
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: IDENTIFIER dimensions_opt
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{ $$ = make_port_list($1, $2, 0); }
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| IDENTIFIER dimensions_opt '=' expression
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{ $$ = make_port_list($1, $2, $4); }
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| list_of_variable_port_identifiers ',' IDENTIFIER dimensions_opt
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{ $$ = make_port_list($1, $3, $4, 0); }
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| list_of_variable_port_identifiers ',' IDENTIFIER dimensions_opt '=' expression
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{ $$ = make_port_list($1, $3, $4, $6); }
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;
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@ -4652,58 +4659,102 @@ module_item
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delete $4;
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}
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| attribute_list_opt port_direction unsigned_signed_opt dimensions_opt delay3_opt list_of_identifiers ';'
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{ pform_set_port_type(@2, $6, $4, $3, $2, $1); }
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/* The next two rules handle Verilog 2001 statements of the form:
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/* The next two rules handle port declarations that include a net type, e.g.
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input wire signed [h:l] <list>;
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This creates the wire and sets the port type all at once. */
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| attribute_list_opt port_direction net_type unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ pform_makewire(@2, $5, $4, $6, $3, $2, IVL_VT_NO_TYPE, $1, SR_BOTH); }
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| attribute_list_opt port_direction net_type data_type_or_implicit list_of_port_identifiers ';'
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{ pform_module_define_port(@2, $5, $2, $3, $4, $1); }
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| attribute_list_opt K_output var_type unsigned_signed_opt dimensions_opt list_of_port_identifiers ';'
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{ list<pair<perm_string,PExpr*> >::const_iterator pp;
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list<perm_string>*tmp = new list<perm_string>;
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for (pp = $6->begin(); pp != $6->end(); ++ pp ) {
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tmp->push_back((*pp).first);
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}
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pform_makewire(@2, $5, $4, tmp, $3, NetNet::POUTPUT,
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IVL_VT_NO_TYPE, $1, SR_BOTH);
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for (pp = $6->begin(); pp != $6->end(); ++ pp ) {
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if ((*pp).second) {
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pform_make_var_init(@2, (*pp).first, (*pp).second);
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}
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}
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delete $6;
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| attribute_list_opt port_direction K_wreal list_of_port_identifiers ';'
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{ real_type_t*real_type = new real_type_t(real_type_t::REAL);
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pform_module_define_port(@2, $4, $2, NetNet::WIRE, real_type, $1);
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}
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| attribute_list_opt port_direction K_wreal list_of_identifiers ';'
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{ pform_makewire(@2, 0, true, $4, NetNet::WIRE, $2,
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IVL_VT_REAL, $1, SR_BOTH);
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/* The next three rules handle port declarations that include a variable
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type, e.g.
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output reg signed [h:l] <list>;
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and also handle incomplete port declarations, e.g.
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input signed [h:l] <list>;
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*/
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| attribute_list_opt K_inout data_type_or_implicit list_of_port_identifiers ';'
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{ NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
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if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
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if (dtype->implicit_flag)
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use_type = NetNet::NONE;
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}
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if (use_type == NetNet::NONE)
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pform_set_port_type(@2, $4, NetNet::PINOUT, $3, $1);
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else
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pform_module_define_port(@2, $4, NetNet::PINOUT, use_type, $3, $1);
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}
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/* var_type declaration (reg variables) cannot be input or output,
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because the port declaration implies an external driver, which
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cannot be attached to a reg. These rules catch that error early. */
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| attribute_list_opt K_input var_type unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ pform_makewire(@2, $5, $4, $6, $3, NetNet::PINPUT,
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IVL_VT_NO_TYPE, $1);
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yyerror(@3, "error: reg variables cannot be inputs.");
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| attribute_list_opt K_input data_type_or_implicit list_of_port_identifiers ';'
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{ NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
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if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
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if (dtype->implicit_flag)
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use_type = NetNet::NONE;
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}
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if (use_type == NetNet::NONE)
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pform_set_port_type(@2, $4, NetNet::PINPUT, $3, $1);
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else
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pform_module_define_port(@2, $4, NetNet::PINPUT, use_type, $3, $1);
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}
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| attribute_list_opt K_inout var_type unsigned_signed_opt dimensions_opt list_of_identifiers ';'
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{ pform_makewire(@2, $5, $4, $6, $3, NetNet::PINOUT,
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IVL_VT_NO_TYPE, $1);
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yyerror(@3, "error: reg variables cannot be inouts.");
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| attribute_list_opt K_output data_type_or_implicit list_of_variable_port_identifiers ';'
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{ NetNet::Type use_type = $3 ? NetNet::IMPLICIT : NetNet::NONE;
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if (vector_type_t*dtype = dynamic_cast<vector_type_t*> ($3)) {
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if (dtype->implicit_flag)
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use_type = NetNet::NONE;
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else if (dtype->reg_flag)
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use_type = NetNet::REG;
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else
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use_type = NetNet::IMPLICIT_REG;
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// The SystemVerilog types that can show up as
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// output ports are implicitly (on the inside)
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// variables because "reg" is not valid syntax
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// here.
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} else if (dynamic_cast<atom2_type_t*> ($3)) {
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use_type = NetNet::IMPLICIT_REG;
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} else if (dynamic_cast<struct_type_t*> ($3)) {
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use_type = NetNet::IMPLICIT_REG;
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} else if (enum_type_t*etype = dynamic_cast<enum_type_t*> ($3)) {
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if(etype->base_type == IVL_VT_LOGIC)
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use_type = NetNet::IMPLICIT_REG;
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}
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if (use_type == NetNet::NONE)
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pform_set_port_type(@2, $4, NetNet::POUTPUT, $3, $1);
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else
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pform_module_define_port(@2, $4, NetNet::POUTPUT, use_type, $3, $1);
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}
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| attribute_list_opt port_direction unsigned_signed_opt dimensions_opt delay3_opt error ';'
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| attribute_list_opt port_direction net_type data_type_or_implicit error ';'
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{ yyerror(@2, "error: Invalid variable list in port declaration.");
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if ($1) delete $1;
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if ($4) delete $4;
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if ($5) delete $5;
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yyerrok;
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}
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| attribute_list_opt K_inout data_type_or_implicit error ';'
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{ yyerror(@2, "error: Invalid variable list in port declaration.");
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if ($1) delete $1;
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if ($3) delete $3;
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yyerrok;
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}
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| attribute_list_opt K_input data_type_or_implicit error ';'
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{ yyerror(@2, "error: Invalid variable list in port declaration.");
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if ($1) delete $1;
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if ($3) delete $3;
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yyerrok;
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}
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| attribute_list_opt K_output data_type_or_implicit error ';'
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{ yyerror(@2, "error: Invalid variable list in port declaration.");
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if ($1) delete $1;
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if ($3) delete $3;
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yyerrok;
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}
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@ -5103,10 +5154,6 @@ net_type
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| K_uwire { $$ = NetNet::UNRESOLVED_WIRE; }
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;
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var_type
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: K_reg { $$ = NetNet::REG; }
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;
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param_type
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: bit_logic_opt unsigned_signed_opt dimensions_opt
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{ param_active_range = $3;
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84
pform.cc
84
pform.cc
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@ -1944,6 +1944,7 @@ static void pform_set_net_range(perm_string name,
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VLerror("error: name is not a valid net.");
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return;
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}
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// If this is not implicit ("implicit" meaning we don't
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// know what the type is yet) then set the type now.
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if (net_type != NetNet::IMPLICIT && net_type != NetNet::NONE) {
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@ -2349,7 +2350,8 @@ void pform_module_define_port(const struct vlltype&li,
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NetNet::PortType port_kind,
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NetNet::Type type,
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data_type_t*vtype,
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list<named_pexpr_t>*attr)
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list<named_pexpr_t>*attr,
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bool keep_attr)
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{
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struct_type_t*struct_type = 0;
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ivl_variable_type_t data_type = IVL_VT_NO_TYPE;
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@ -2438,10 +2440,37 @@ void pform_module_define_port(const struct vlltype&li,
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cur->set_unpacked_idx(*urange);
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}
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pform_bind_attributes(cur->attributes, attr);
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pform_bind_attributes(cur->attributes, attr, keep_attr);
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pform_put_wire_in_scope(name, cur);
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}
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void pform_module_define_port(const struct vlltype&li,
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list<pform_port_t>*ports,
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NetNet::PortType port_kind,
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NetNet::Type type,
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data_type_t*vtype,
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list<named_pexpr_t>*attr)
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{
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for (list<pform_port_t>::iterator cur = ports->begin()
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; cur != ports->end() ; ++ cur ) {
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data_type_t*use_type = vtype;
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if (cur->udims)
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use_type = new uarray_type_t(vtype, cur->udims);
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pform_module_define_port(li, cur->name, port_kind, type, use_type,
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attr, true);
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if (cur->udims)
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delete use_type;
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if (cur->expr)
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pform_make_var_init(li, cur->name, cur->expr);
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}
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delete ports;
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delete attr;
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}
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/*
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* This function makes a single signal (a wire, a reg, etc) as
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* requested by the parser. The name is unscoped, so I attach the
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@ -3246,24 +3275,53 @@ static void pform_set_port_type(perm_string name, NetNet::PortType pt,
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}
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void pform_set_port_type(const struct vlltype&li,
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list<perm_string>*names,
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list<pform_range_t>*range,
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bool signed_flag,
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list<pform_port_t>*ports,
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NetNet::PortType pt,
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data_type_t*dt,
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list<named_pexpr_t>*attr)
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{
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assert(pt != NetNet::PIMPLICIT && pt != NetNet::NOT_A_PORT);
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for (list<perm_string>::iterator cur = names->begin()
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; cur != names->end() ; ++ cur ) {
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perm_string txt = *cur;
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pform_set_port_type(txt, pt, li.text, li.first_line);
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pform_set_net_range(txt, NetNet::NONE, range, signed_flag, IVL_VT_NO_TYPE,
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SR_PORT, attr);
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list<pform_range_t>*range = 0;
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bool signed_flag = false;
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if (vector_type_t*vt = dynamic_cast<vector_type_t*> (dt)) {
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assert(vt->implicit_flag);
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range = vt->pdims.get();
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signed_flag = vt->signed_flag;
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} else {
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assert(dt == 0);
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}
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delete names;
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delete range;
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bool have_init_expr = false;
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for (list<pform_port_t>::iterator cur = ports->begin()
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; cur != ports->end() ; ++ cur ) {
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pform_set_port_type(cur->name, pt, li.text, li.first_line);
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pform_set_net_range(cur->name, NetNet::NONE, range, signed_flag,
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IVL_VT_NO_TYPE, SR_PORT, attr);
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if (cur->udims) {
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cerr << li.text << ":" << li.first_line << ": warning: "
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<< "Array dimensions in incomplete port declarations "
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<< "are currently ignored." << endl;
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cerr << li.text << ":" << li.first_line << ": : "
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<< "The dimensions specified in the net or variable "
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<< "declaration will be used." << endl;
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delete cur->udims;
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}
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if (cur->expr) {
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have_init_expr = true;
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delete cur->expr;
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}
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}
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if (have_init_expr) {
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cerr << li.text << ":" << li.first_line << ": error: "
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<< "Incomplete port declarations cannot be initialized."
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<< endl;
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error_count += 1;
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}
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delete ports;
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delete dt;
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delete attr;
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}
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25
pform.h
25
pform.h
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@ -168,14 +168,21 @@ extern void pform_startmodule(const struct vlltype&loc, const char*name,
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extern void pform_check_timeunit_prec();
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extern void pform_module_set_ports(vector<Module::port_t*>*);
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/* This function is used to support the port definition in a
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port_definition_list. In this case, we have everything needed to
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define the port, all in one place. */
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/* These functions are used when we have a complete port definition, either
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in an ansi style or non-ansi style declaration. In this case, we have
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everything needed to define the port, all in one place. */
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extern void pform_module_define_port(const struct vlltype&li,
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perm_string name,
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NetNet::PortType,
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NetNet::Type type,
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data_type_t*vtype,
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list<named_pexpr_t>*attr,
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bool keep_attr =false);
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extern void pform_module_define_port(const struct vlltype&li,
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list<pform_port_t>*ports,
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NetNet::PortType,
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NetNet::Type type,
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data_type_t*vtype,
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list<named_pexpr_t>*attr);
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extern Module::port_t* pform_module_port_reference(perm_string name,
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@ -364,14 +371,14 @@ extern void pform_makewire(const struct vlltype&li,
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extern void pform_make_var_init(const struct vlltype&li,
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perm_string name, PExpr*expr);
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/* Look up the names of the wires, and set the port type,
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i.e. input, output or inout. If the wire does not exist, create
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it. The second form takes a single name. */
|
||||
/* This function is used when we have an incomplete port definition in
|
||||
a non-ansi style declaration. Look up the names of the wires, and set
|
||||
the port type, i.e. input, output or inout, and, if specified, the
|
||||
range and signedness. If the wire does not exist, create it. */
|
||||
extern void pform_set_port_type(const struct vlltype&li,
|
||||
list<perm_string>*names,
|
||||
list<pform_range_t>*range,
|
||||
bool signed_flag,
|
||||
list<pform_port_t>*ports,
|
||||
NetNet::PortType,
|
||||
data_type_t*dt,
|
||||
list<named_pexpr_t>*attr);
|
||||
|
||||
extern void pform_set_reg_idx(perm_string name,
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#ifndef IVL_pform_types_H
|
||||
#define IVL_pform_types_H
|
||||
/*
|
||||
* Copyright (c) 2007-2014 Stephen Williams (steve@icarus.com)
|
||||
* Copyright (c) 2007-2016 Stephen Williams (steve@icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
|
|
@ -72,6 +72,21 @@ typedef named<PExpr*> named_pexpr_t;
|
|||
*/
|
||||
typedef std::pair<PExpr*,PExpr*> pform_range_t;
|
||||
|
||||
/*
|
||||
* The pform_port_t holds the name and optional unpacked dimensions
|
||||
* and initialization expression for a single port in a list of port
|
||||
* declarations.
|
||||
*/
|
||||
struct pform_port_t {
|
||||
pform_port_t(perm_string n, list<pform_range_t>*ud, PExpr*e)
|
||||
: name(n), udims(ud), expr(e) { }
|
||||
~pform_port_t() { }
|
||||
|
||||
perm_string name;
|
||||
list<pform_range_t>*udims;
|
||||
PExpr*expr;
|
||||
};
|
||||
|
||||
/*
|
||||
* Semantic NOTES:
|
||||
* - The SEL_BIT is a single expression. This might me a bit select
|
||||
|
|
|
|||
Loading…
Reference in New Issue