luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Connect module instance arrays MSB to MSB. 

When a bit port of a module instance is connected to a vector
argument, the MSB module instance should be connected to the MSB
of the vector argument. This matters only in the rare case that
the %m is used. It also makes wave dumps come out right.
This commit is contained in:
Stephen Williams 2008-03-06 20:37:08 -08:00
parent 8d3febff2b
commit 692caca9dc
2 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
elab_scope.cc
View File

@ -741,7 +741,11 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
/* Stash the instance array of scopes into the parent /* Stash the instance array of scopes into the parent
scope. Later elaboration passes will use this vector to scope. Later elaboration passes will use this vector to
further elaborate the array. */ further elaborate the array.
Note that the array is ordered from LSB to MSB. We will use
that fact in the main elaborate to connect things in the
correct order. */
sc->instance_arrays[get_name()] = instances; sc->instance_arrays[get_name()] = instances;
} }

4
elaborate.cc
View File

@ -1037,7 +1037,9 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
unsigned prts_vector_width = 0; unsigned prts_vector_width = 0;
for (unsigned inst = 0 ; inst < instance.count() ; inst += 1) { for (unsigned inst = 0 ; inst < instance.count() ; inst += 1) {
NetScope*inst_scope = instance[inst]; // Scan the instances from MSB to LSB. The port
// will be assembled in that order as well.
NetScope*inst_scope = instance[instance.count()-inst-1];
// Scan the module sub-ports for this instance... // Scan the module sub-ports for this instance...
for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) { for (unsigned ldx = 0 ; ldx < mport.count() ; ldx += 1) {