Fix expansion of unbased unsized literal in port assignment (issue #756)
(cherry picked from commit 310e239637)
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elaborate.cc
18
elaborate.cc
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@ -1472,17 +1472,23 @@ void PGModule::elaborate_mod_(Design*des, Module*rmod, NetScope*scope) const
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continue;
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continue;
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}
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}
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/* Input to module. elaborate the expression to
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/* Input to module. Here we elaborate the source expression
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the desired width. If this in an instance
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using its self-determined width. This allows us to check
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array, then let the net determine its own
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for and warn about port width mismatches. But in the
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width. We use that, then, to decide how to hook
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special case that the source expression is a SV unbased
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it up.
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unsized literal, we need to force the expression width
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to match the destination.
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NOTE that this also handles the case that the
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NOTE that this also handles the case that the
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port is actually empty on the inside. We assume
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port is actually empty on the inside. We assume
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in that case that the port is input. */
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in that case that the port is input. */
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NetExpr*tmp_expr = elab_and_eval(des, scope, pins[idx], -1);
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int context_width = -1;
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if (PENumber*literal = dynamic_cast<PENumber*>(pins[idx])) {
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if (literal->value().is_single())
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context_width = prts_vector_width;
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}
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NetExpr*tmp_expr = elab_and_eval(des, scope, pins[idx], context_width);
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if (tmp_expr == 0) {
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if (tmp_expr == 0) {
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cerr << pins[idx]->get_fileline()
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cerr << pins[idx]->get_fileline()
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<< ": error: Failed to elaborate port expression."
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<< ": error: Failed to elaborate port expression."
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