Spelling fixes (larry doolittle)

tgt-fpga/configure.in

@@ -17,7 +17,7 @@ AC_CHECK_HEADERS(malloc.h)
 # may modify CPPFLAGS and CFLAGS
 AX_CPP_PRECOMP
 
-# Compiler option for position independent code, needed whan making shared objects.
+# Compiler option for position independent code, needed when making shared objects.
 AX_C_PICFLAG
 
 # linker options when building a shared library

tgt-fpga/device.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: device.h,v 1.14 2003/11/12 03:20:14 steve Exp $"
+#ident "$Id: device.h,v 1.15 2007/02/26 19:49:49 steve Exp $"
 #endif
 
 # include  <ivl_target.h>
@@ -72,7 +72,7 @@ struct device_s {
  * Return the device_t cookie given the name of the architecture. If
  * the device is not found, return 0.
  *
- * This function is used if the user specifies the archetecture
+ * This function is used if the user specifies the architecture
  * explicitly, with the -parch=name flag.
  */
 extern device_t device_from_arch(const char*arch);
@@ -80,6 +80,9 @@ extern device_t device_from_arch(const char*arch);
 
 /*
  * $Log: device.h,v $
+ * Revision 1.15  2007/02/26 19:49:49  steve
+ *  Spelling fixes (larry doolittle)
+ *
  * Revision 1.14  2003/11/12 03:20:14  steve
  *  devices need show_cmp_gt
  *

tgt-fpga/edif.h

@@ -19,7 +19,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: edif.h,v 1.7 2003/09/03 23:34:09 steve Exp $"
+#ident "$Id: edif.h,v 1.8 2007/02/26 19:49:49 steve Exp $"
 #endif
 
 # include  <stdio.h>
@@ -47,7 +47,7 @@
  *
  *   Declare external libraries with edif_xlibrary_create
  *     Normally, this is the single technology library that contains
- *     the primitive cells that the code generator intendes to
+ *     the primitive cells that the code generator intends to
  *     use. The library is given a name, such as VIRTEX or whatever
  *     the implementation tools expect. Cells are attached to the
  *     library later. An edif netlist may include multiple external
@@ -196,7 +196,7 @@ extern edif_cellref_t edif_cellref_create(edif_t edf, edif_cell_t cell);
 
 /* Instances can have properties attached to them. The name and value
    given here are turned into a (property <name> (string "val"))
-   sexpression attached to the instance.
+   expression attached to the instance.
 
    Examples of string properties commonly attached to cellref devices
    include such things as the INIT=<value> to initialize LUT cells in
@@ -231,6 +231,9 @@ extern void edif_print(FILE*fd, edif_t design);
 
 /*
  * $Log: edif.h,v $
+ * Revision 1.8  2007/02/26 19:49:49  steve
+ *  Spelling fixes (larry doolittle)
+ *
  * Revision 1.7  2003/09/03 23:34:09  steve
  *  Support synchronous set of LPM_FF devices.
  *

tgt-fpga/xilinx.c

@@ -17,7 +17,7 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: xilinx.c,v 1.12 2004/02/15 18:03:30 steve Exp $"
+#ident "$Id: xilinx.c,v 1.13 2007/02/26 19:49:50 steve Exp $"
 #endif
 
 # include  "edif.h"
@@ -273,7 +273,7 @@ edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
 
 /*
  * This function does a lot of the stuff common to the header
- * functions of various Xilinx familes. This includes creating the edf
+ * functions of various Xilinx families. This includes creating the edf
  * object that holds the netlist.
  */
 void xilinx_common_header(ivl_design_t des)
@@ -835,14 +835,14 @@ void xilinx_shiftl(ivl_lpm_t net)
 
 	/* Allocate a matrix of edif_cellref_t variables. A devices
 	   will be addressed by the expression table[sdx][qdx];
-	   This should make the algorighm code easier to read. */
+	   This should make the algorithm code easier to read. */
       cells = calloc(nsel * width, sizeof(edif_cellref_t));
       table = calloc(nsel, sizeof(edif_cellref_t*));
 
       for (sdx = 0 ;  sdx < nsel ;  sdx += 1)
 	    table[sdx] = cells + sdx*width;
 
-	/* Make a 0 valued pad bit. I wlil use this for all the shifin
+	/* Make a 0 valued pad bit. I will use this for all the shift in
 	   values that are beyond the input. */
       pad0_cell = edif_cellref_create(edf, cell_0);
       pad0 = edif_joint_create(edf);
@@ -951,6 +951,9 @@ void xilinx_shiftl(ivl_lpm_t net)
 
 /*
  * $Log: xilinx.c,v $
+ * Revision 1.13  2007/02/26 19:49:50  steve
+ *  Spelling fixes (larry doolittle)
+ *
  * Revision 1.12  2004/02/15 18:03:30  steve
  *  Cleanup of warnings.
  *

tgt-fpga/xilinx.h

@@ -19,13 +19,13 @@
  *    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
  */
 #ifdef HAVE_CVS_IDENT
-#ident "$Id: xilinx.h,v 1.8 2003/08/15 02:23:53 steve Exp $"
+#ident "$Id: xilinx.h,v 1.9 2007/02/26 19:49:50 steve Exp $"
 #endif
 
 /*
  * This header file includes XILINX library support functions. They
  * manage the creation and reference of cells from the library. Use
- * the xililx_cell_* functions to get an edif_cell_t from the
+ * the xilinx_cell_* functions to get an edif_cell_t from the
  * library. The function will create the cell in the library if
  * needed, or will return the existing cell if it was already called.
  */
@@ -130,6 +130,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
 
 /*
  * $Log: xilinx.h,v $
+ * Revision 1.9  2007/02/26 19:49:50  steve
+ *  Spelling fixes (larry doolittle)
+ *
  * Revision 1.8  2003/08/15 02:23:53  steve
  *  Add synthesis support for synchronous reset.
  *