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Remove some uneccessary zero-time waits from VHDL outputs

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This patch optimises away straight line sequences like:

wait for 0 ns;
wait for X ns;

to:

wait for X ns;

This tidies up the output a bit.

It also has the effect of removing all code from initial
processes where the assignments have been extracted as
VHDL signal intialisers. (c.f. pr2391337)
This commit is contained in:
Nick Gasson
2008-12-07 16:53:47 -08:00
committed by Stephen Williams
parent 712e08ebe8
commit 651d208451
5 changed files with 43 additions and 7 deletions
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tgt-vhdl/process.cc
+9 -4
View File
@@ -56,10 +56,15 @@ static int generate_vhdl_process(vhdl_entity *ent, ivl_process_t proc)
// However, if no statements were added to the container
// by draw_stmt, don't bother adding a wait as `emit'
// will optimise the process out of the output
if (ivl_process_type(proc) == IVL_PR_INITIAL
&& !vhdl_proc->get_container()->empty()) {
vhdl_wait_stmt *wait = new vhdl_wait_stmt();
vhdl_proc->get_container()->add_stmt(wait);
if (ivl_process_type(proc) == IVL_PR_INITIAL) {
// Get rid of any useless `wait for 0 ns's at the end of the process
prune_wait_for_0(vhdl_proc->get_container());
// The above pruning might have removed all logic from the process
if (!vhdl_proc->get_container()->empty()) {
vhdl_wait_stmt *wait = new vhdl_wait_stmt();
vhdl_proc->get_container()->add_stmt(wait);
}
}
// Add a comment indicating where it came from