luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix casting/resizing order bug

This commit is contained in:
Nick Gasson 2008-06-23 15:00:55 +01:00
parent 449cd0a76e
commit 632a265e14
1 changed files with 12 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
tgt-vhdl/vhdl_syntax.cc
View File

@ -486,15 +486,17 @@ vhdl_expr *vhdl_expr::cast(const vhdl_type *to)
return conv; return conv;
} }
else { else {
vhdl_expr *tocast = this; // We have to cast the expression before resizing or the
if (to->get_width() != type_->get_width()) // wrong sign bit may be extended (i.e. when casting between
tocast = resize(to->get_width()); // signed/unsigned *and* resizing)
vhdl_fcall *conv = vhdl_fcall *conv =
new vhdl_fcall(to->get_string().c_str(), new vhdl_type(*to)); new vhdl_fcall(to->get_string().c_str(), new vhdl_type(*to));
conv->add_expr(tocast); conv->add_expr(this);
return conv; if (to->get_width() != type_->get_width())
return conv->resize(to->get_width());
else
return conv;
} }
} }
@ -613,11 +615,12 @@ vhdl_const_bits::vhdl_const_bits(const char *value, int width, bool issigned)
qualified_(false), qualified_(false),
signed_(issigned) signed_(issigned)
{ {
std::cout << (issigned ? "signed" : "unsigned") << " bits" << std::endl;
// Can't rely on value being NULL-terminated // Can't rely on value being NULL-terminated
while (width--) while (width--)
value_.push_back(*value++); value_.push_back(*value++);
std::cout << (issigned ? "signed" : "unsigned") << " bits: "
<< value_ << std::endl;
} }
vhdl_expr *vhdl_const_bits::cast(const vhdl_type *to) vhdl_expr *vhdl_const_bits::cast(const vhdl_type *to)