Handle constant indexed part selects.
This commit is contained in:
parent
c1b73c83f4
commit
5e067bd651
22
elab_expr.cc
22
elab_expr.cc
|
|
@ -3238,26 +3238,32 @@ NetExpr* PEIdent::elaborate_expr_net_idx_up_(Design*des, NetScope*scope,
|
||||||
NetExpr*ex;
|
NetExpr*ex;
|
||||||
if (base_c->value().is_defined()) {
|
if (base_c->value().is_defined()) {
|
||||||
long lsv = base_c->value().as_long();
|
long lsv = base_c->value().as_long();
|
||||||
|
long offset = 0;
|
||||||
|
// Get the signal range.
|
||||||
|
const list<NetNet::range_t>&packed = net->sig()->packed_dims();
|
||||||
|
ivl_assert(*this, packed.size() == prefix_indices.size()+1);
|
||||||
|
|
||||||
|
// We want the last range, which is where we work.
|
||||||
|
const NetNet::range_t&rng = packed.back();
|
||||||
|
if (rng.msb < rng.lsb) {
|
||||||
|
offset = -wid + 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
long rel_base = net->sig()->sb_to_idx(prefix_indices, lsv);
|
||||||
|
|
||||||
// If the part select covers exactly the entire
|
// If the part select covers exactly the entire
|
||||||
// vector, then do not bother with it. Return the
|
// vector, then do not bother with it. Return the
|
||||||
// signal itself.
|
// signal itself.
|
||||||
if (net->sig()->sb_to_idx(prefix_indices, lsv) == 0 &&
|
if (rel_base == 0 && wid == net->vector_width()) {
|
||||||
wid == net->vector_width()) {
|
|
||||||
delete base;
|
delete base;
|
||||||
net->cast_signed(false);
|
net->cast_signed(false);
|
||||||
return net;
|
return net;
|
||||||
}
|
}
|
||||||
|
|
||||||
long offset = 0;
|
|
||||||
if (net->msi() < net->lsi()) {
|
|
||||||
offset = -wid + 1;
|
|
||||||
}
|
|
||||||
// Otherwise, make a part select that covers the right
|
// Otherwise, make a part select that covers the right
|
||||||
// range.
|
// range.
|
||||||
ex = new NetEConst(verinum(net->sig()->sb_to_idx(prefix_indices,lsv) + offset));
|
ex = new NetEConst(verinum(rel_base + offset));
|
||||||
if (warn_ob_select) {
|
if (warn_ob_select) {
|
||||||
long rel_base = net->sig()->sb_to_idx(prefix_indices,lsv) + offset;
|
|
||||||
if (rel_base < 0) {
|
if (rel_base < 0) {
|
||||||
cerr << get_fileline() << ": warning: "
|
cerr << get_fileline() << ": warning: "
|
||||||
<< net->name();
|
<< net->name();
|
||||||
|
|
|
||||||
|
|
@ -543,11 +543,12 @@ bool PEIdent::elaborate_lval_net_idx_(Design*des,
|
||||||
if (base_c->value().is_defined()) {
|
if (base_c->value().is_defined()) {
|
||||||
long lsv = base_c->value().as_long();
|
long lsv = base_c->value().as_long();
|
||||||
long offset = 0;
|
long offset = 0;
|
||||||
// This is a work-around for limited dimenions support.
|
// Get the signal range.
|
||||||
const list<NetNet::range_t>&packed = reg->packed_dims();
|
const list<NetNet::range_t>&packed = reg->packed_dims();
|
||||||
ivl_assert(*this, packed.size() == 1);
|
ivl_assert(*this, packed.size() == prefix_indices.size()+1);
|
||||||
const NetNet::range_t&rng = packed.back();
|
|
||||||
|
|
||||||
|
// We want the last range, which is where we work.
|
||||||
|
const NetNet::range_t&rng = packed.back();
|
||||||
if (((rng.msb < rng.lsb) &&
|
if (((rng.msb < rng.lsb) &&
|
||||||
use_sel == index_component_t::SEL_IDX_UP) ||
|
use_sel == index_component_t::SEL_IDX_UP) ||
|
||||||
((rng.msb > rng.lsb) &&
|
((rng.msb > rng.lsb) &&
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue