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iverilog with an iverilog.conf configuration file.
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.TH iverilog 1 "$Date: 2000/10/08 22:36:56 $" Version "$Date: 2000/10/08 22:36:56 $"
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.SH NAME
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iverilog - Icarus Verilog compiler
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.SH SYNOPSIS
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.B iverilog
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[-ESv] [-Dmacro[=defn]] [-fflag=value] [-Iincludepath] [-mmodule] [-Nfile] [-ooutputfilename] [-s topmodule] [-ttype] [-Tmin/typ/max] [-Wclass] sourcefile[s]
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.SH DESCRIPTION
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.PP
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\fIiverilog\fP is a compiler that translates Verilog source code into
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executable programs for simulation, or other netlist formats for
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further processing. The currenty supported targets are \fIvvm\fP (for
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executable simulation) and \fIxnf\fP for synthesis. Other target
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types are added as code generators are implemented.
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.SH OPTIONS
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.l
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\fIiverilog\fP accepts the following options:
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.TP 8
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.B -B\fIbase\fP
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The \fIiverilog\fP program uses external programs to preprocess and
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compile the verilog source. Normally, the path used to locate these
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tools is built into the \fIiverilog\fP program. However, the \fB-B\fP
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switch allows the user to select a different set of programs. The path
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given is used to locate \fIivlpp\fP, \fIivl\fP and the VPI modules.
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.TP 8
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.B -D\fImacro\fP
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Defines macro \fImacro\fP with the string `1' as its definition. This
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form is normally only used to trigger ifdef conditionals in the
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Verilog source.
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.TP 8
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.B -D\fImacro=defn\fP
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Defines macro \fImacro\fP as \fIdefn\fP.
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.TP 8
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.B -E
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Preprocess the Verilog source, but do not compile it. The output file
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is the Verilog input, but with file inclusions and macro references
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expanded and removed. This is useful, for example, to preprocess
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verilog source for use by other compilers.
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.TP 8
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.B -f\fIflag=value\fP
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Assign a value to a target specific flag. The \fB-f\fP switch may be
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used as often as necessary to specify all the desired flags. The flags
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that are used depend on the target that is selected, and are described
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in target specific documentation. Flags that are not used are ignored.
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.TP 8
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.B -I\fIincludedir\fP
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Append directory \fIincludepdir\fP to list of directoriess searched
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for Verilog include files. The \fB-I\fP switch may be used many times
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to specify several directories to search, the directories are searched
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in the order they appear on the command line.
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.TP 8
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.B -m\fImodule\fP
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Add this module to the list of VPI modules to be loaded by the
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simulation. Many modules can be specified, and all will be loaded, in
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the order specified.
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.TP 8
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.B -N\fIpath\fP
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This is used for debugging the compiler proper. Dump the final netlist
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form of the design to the specified file. It otherwise does not affect
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operation of the compiler. The dump happens after the design is
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elaborated and optimized.
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.TP 8
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.B -o \fIfilename\fP
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Place output in the file \fIfilename\fP. If no output file name is
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specified, \fIiverilog\fP uses the default name \fBa.out\fP.
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.TP 8
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.B -S
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Synthesize. Normally, if the target can accept behavioral
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descriptions the compiler will leave processes in behavioral
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form. The \fB-S\fP switch causes the compiler to perform synthesis
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even if it is not necessary for the target. If the target type is a
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netlist format, the \fB-S\fP switch is unnecessary and has no effect.
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.TP 8
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.B -s \fItopmodule\fP
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Specify the top level module to elaborate. Icarus Verilog will by default
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choose the only module that has no ports. However, this simplistic
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heuristic is often not sufficient, and sometimes not what is wanted
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anyhow.
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.TP 8
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.B -T\fImin|typ|max\fP
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Use this switch to select min, typ or max times from min:typ:max
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expressions. Normally, the compiler will simply use the typ value from
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these expressions (with a warning) but this switch will tell the
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compiler explicitly which value to use. This will suppress the
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warning that the compiler is making a choice.
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.TP 8
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.B -t\fItarget\fP
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Use this switch to specify the target output format. See the
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\fBTARGETS\fP section below for a list of valid output formats.
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.TP 8
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.B -v
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Turn on verbose messages. This will print the command lines that are
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executed to perform the actual compilation, along with version
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information from the various components.
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.TP 8
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.B -W\fIclass\fP
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Turn on different classes of warnings. See the \fBWARNING TYPES\fP
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section below for desctriptions of the different warning groups. If
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multiple \fB-W\fP switches are used, the warning set is the union of
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all the requested classes.
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.SH TARGETS
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The Icarus Verilog compiler supports a variety of targets, for
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different purposes, and the \fB-t\fP switch is used to select the
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desired target.
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.TP 8
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.B null
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The null target causes no code to be generated. It is useful for
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checking the syntax of the Verilog source.
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.TP 8
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.B vvm
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This is the default. The target is an executable program that uses the
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vvm simulation runtime. The compiler actually generates C++ code, then
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compiles and links that code to make the output executable.
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.TP 8
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.B xnf
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This is the Xilinx Netlist Format used by many tools for placing
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devices in FPGAs or other programmable devices. The Icarus Verilog XNF
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code generator can generate complete designs or XNF macros that can be
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imported into larger designs by other tools.
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.SH "WARNING TYPES"
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These are the types of warnings that can be selected by the \fB-W\fP
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switch.
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.TP 8
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.B all
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This enables all supported warning categories.
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.TP 8
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.B implicit
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This enables warnings for creation of implicit declarations. For
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example, if a scaler wire X is used but not declared in the Verilog
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source, this will print a warning at its first use.
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.SH EXAMPLES
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These examples assume that you have a Verilog source file called hello.v in
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the current directory
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To compile hello.v to an executable file called a.out:
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verilog hello.v
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To compile hello.v to an executable file called hello:
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verilog -o hello hello.v
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To compile hello.v to a file in XNF-format called hello.xnf
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verilog -txnf -ohello.xnf hello.v
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.SH "AUTHOR"
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.nf
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Steve Williams ([email protected])
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.SH SEE ALSO
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.BR "<http://www.icarus.com/eda/verilog/>"
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.SH COPYRIGHT
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.nf
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Copyright \(co 2000 Stephen Williams
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This document can be freely redistributed according to the terms of the
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GNU General Public License version 2.0
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