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Bitwise AND

This commit is contained in:
Nick Gasson 2008-06-21 15:05:48 +01:00
parent 0caf4fd9d0
commit 58f2f5007d
1 changed files with 2 additions and 0 deletions
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2
tgt-vhdl/expr.cc
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@ -165,6 +165,8 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
rhs->cast(&std_logic_vector), VHDL_BINOP_NEQ); rhs->cast(&std_logic_vector), VHDL_BINOP_NEQ);
else else
return translate_relation(lhs, rhs, VHDL_BINOP_NEQ); return translate_relation(lhs, rhs, VHDL_BINOP_NEQ);
case '&': // Bitwise AND
return translate_numeric(lhs, rhs, VHDL_BINOP_AND);
case 'o': case 'o':
return translate_relation(lhs, rhs, VHDL_BINOP_OR); return translate_relation(lhs, rhs, VHDL_BINOP_OR);
default: default: