luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Pad operands of bitwise operators. 

When elaborating bitwise operators width context determined width,
pad the operands.
This commit is contained in:
Stephen Williams 2008-09-30 21:35:09 -07:00
parent b548dec070
commit 55a15d604d
3 changed files with 20 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
PExpr.h
View File

@ -467,6 +467,7 @@ class PEBinary : public PExpr {
NetExpr*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const; NetExpr*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_eval_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const; NetExpr*elaborate_eval_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_bits_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_div_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const; NetExpr*elaborate_expr_base_div_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_lshift_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const; NetExpr*elaborate_expr_base_lshift_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetExpr*elaborate_expr_base_rshift_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const; NetExpr*elaborate_expr_base_rshift_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;

20
elab_expr.cc
View File

@ -298,8 +298,7 @@ NetExpr* PEBinary::elaborate_expr_base_(Design*des,
case 'O': // NOR (~|) case 'O': // NOR (~|)
case 'A': // NAND (~&) case 'A': // NAND (~&)
case 'X': case 'X':
tmp = new NetEBBits(op_, lp, rp); tmp = elaborate_expr_base_bits_(des, lp, rp, expr_wid);
tmp->set_line(*this);
break; break;
case '+': case '+':
@ -352,6 +351,23 @@ NetExpr* PEBinary::elaborate_expr_base_(Design*des,
return tmp; return tmp;
} }
NetExpr* PEBinary::elaborate_expr_base_bits_(Design*des,
NetExpr*lp, NetExpr*rp,
int expr_wid) const
{
if (expr_wid > 0) {
if (type_is_vectorable(lp->expr_type()))
lp = pad_to_width(lp, expr_wid);
if (type_is_vectorable(rp->expr_type()))
rp = pad_to_width(rp, expr_wid);
}
NetEBBits*tmp = new NetEBBits(op_, lp, rp);
tmp->set_line(*this);
return tmp;
}
NetExpr* PEBinary::elaborate_expr_base_div_(Design*des, NetExpr* PEBinary::elaborate_expr_base_div_(Design*des,
NetExpr*lp, NetExpr*rp, NetExpr*lp, NetExpr*rp,
int expr_wid) const int expr_wid) const

2
expr_synth.cc
View File

@ -164,7 +164,7 @@ NetNet* NetEBBits::synthesize(Design*des, NetScope*scope)
return 0; return 0;
} }
unsigned width = lsig->vector_width(); unsigned width = expr_width();
if (rsig->vector_width() > width) width = rsig->vector_width(); if (rsig->vector_width() > width) width = rsig->vector_width();
lsig = pad_to_width(des, lsig, width); lsig = pad_to_width(des, lsig, width);