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Refactor signdness changing code into a single function 

This is the code that generated calls to signed/unsigned in
the VHDL output.
This commit is contained in:
Nick Gasson 2008-07-08 13:07:11 +01:00
parent 1cd7689d03
commit 55747bf79d
1 changed files with 16 additions and 30 deletions
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46
tgt-vhdl/expr.cc
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@ -23,6 +23,18 @@
#include <iostream> #include <iostream>
#include <cassert> #include <cassert>
/*
* Change the signdness of a vector.
*/
static vhdl_expr *change_signdness(vhdl_expr *e, bool issigned)
{
int msb = e->get_type()->get_msb();
int lsb = e->get_type()->get_lsb();
vhdl_type u(issigned ? VHDL_TYPE_SIGNED : VHDL_TYPE_UNSIGNED, msb, lsb);
return e->cast(&u);
}
/* /*
* Convert a constant Verilog string to a constant VHDL string. * Convert a constant Verilog string to a constant VHDL string.
*/ */
@ -75,31 +87,13 @@ static vhdl_expr *translate_unary(ivl_expr_t e)
//operand->print(); //operand->print();
//std::cout << "^ should be signed but is not" << std::endl; //std::cout << "^ should be signed but is not" << std::endl;
int msb = operand->get_type()->get_msb(); operand = change_signdness(operand, true);
int lsb = operand->get_type()->get_lsb();
vhdl_type u(VHDL_TYPE_SIGNED, msb, lsb);
operand = operand->cast(&u);
} }
else if (operand->get_type()->get_name() == VHDL_TYPE_SIGNED && !should_be_signed) { else if (operand->get_type()->get_name() == VHDL_TYPE_SIGNED && !should_be_signed) {
//operand->print(); //operand->print();
//std::cout << "^ should be unsigned but is not" << std::endl; //std::cout << "^ should be unsigned but is not" << std::endl;
int msb = operand->get_type()->get_msb(); operand = change_signdness(operand, false);
int lsb = operand->get_type()->get_lsb();
vhdl_type u(VHDL_TYPE_UNSIGNED, msb, lsb);
operand = operand->cast(&u);
}
// Need to ensure that the operand is interpreted as unsigned to get VHDL
// to emulate Verilog behaviour
if (operand->get_type()->get_name() == VHDL_TYPE_SIGNED) {
int msb = operand->get_type()->get_msb();
int lsb = operand->get_type()->get_lsb();
vhdl_type u(VHDL_TYPE_UNSIGNED, msb, lsb);
operand = operand->cast(&u);
} }
char opcode = ivl_expr_opcode(e); char opcode = ivl_expr_opcode(e);
@ -290,21 +284,13 @@ static vhdl_expr *translate_binary(ivl_expr_t e)
//result->print(); //result->print();
//std::cout << "^ should be signed but is not" << std::endl; //std::cout << "^ should be signed but is not" << std::endl;
int msb = result->get_type()->get_msb(); result = change_signdness(result, true);
int lsb = result->get_type()->get_lsb();
vhdl_type u(VHDL_TYPE_SIGNED, msb, lsb);
result = result->cast(&u);
} }
else if (result->get_type()->get_name() == VHDL_TYPE_SIGNED && !should_be_signed) { else if (result->get_type()->get_name() == VHDL_TYPE_SIGNED && !should_be_signed) {
//result->print(); //result->print();
//std::cout << "^ should be unsigned but is not" << std::endl; //std::cout << "^ should be unsigned but is not" << std::endl;
int msb = result->get_type()->get_msb(); result = change_signdness(result, false);
int lsb = result->get_type()->get_lsb();
vhdl_type u(VHDL_TYPE_SIGNED, msb, lsb);
result = result->cast(&u);
} }
int actual_width = result->get_type()->get_width(); int actual_width = result->get_type()->get_width();