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vhdlpp: Minor correction for casting to integer.

This commit is contained in:
Maciej Suminski 2015-01-27 11:00:32 +01:00
parent 48265ecd9b
commit 51ce9f1a60
2 changed files with 3 additions and 8 deletions
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2
vhdlpp/expression.h
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@ -501,7 +501,7 @@ class ExpInteger : public Expression {
void write_to_stream(std::ostream&fd);
int emit(ostream&out, Entity*ent, ScopeBase*scope);
int emit_package(std::ostream&out);
bool is_primary(void) const;
bool is_primary(void) const { return true; }
bool evaluate(ScopeBase*scope, int64_t&val) const;
void dump(ostream&out, int indent = 0) const;
virtual ostream& dump_inline(ostream&out) const;

9
vhdlpp/expression_emit.cc
View File

@ -562,9 +562,9 @@ int ExpFunc::emit(ostream&out, Entity*ent, ScopeBase*scope)
out << ")";
} else if (name_ == "integer" && argv_.size() == 1) {
// Simply skip the function name, SystemVerilog takes care of
// rounding real numbers
out << "$signed(";
errors += argv_[0]->emit(out, ent, scope);
out << ")";
} else if (name_ == "std_logic_vector" && argv_.size() == 1) {
// Special case: The std_logic_vector function casts its
@ -635,11 +635,6 @@ int ExpInteger::emit_package(ostream&out)
return 0;
}
bool ExpInteger::is_primary(void) const
{
return true;
}
int ExpReal::emit(ostream&out, Entity*, ScopeBase*)
{
out << value_;