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Spelling fixes 

mostly comments, but includes some identifiers and message text
This commit is contained in:
Larry Doolittle 2008-01-25 13:34:51 -08:00 committed by Stephen Williams
parent 5ec91ec914
commit 47d65034db
14 changed files with 55 additions and 55 deletions
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2
HName.h
View File

@ -32,7 +32,7 @@ using namespace std;
/*
* This class represents a component of a Verilog hierarchical name. A
* hierarchical component contains a name string (prepresented here
* hierarchical component contains a name string (represented here
* with a perm_string) and an optional signed number. This signed
* number is used if the scope is part of an array, for example an
* array of module instances or a loop generated scope.

10
PExpr.h
View File

@ -119,7 +119,7 @@ class PExpr : public LineInfo {
// Expressions that can be in the l-value of procedural
// assignments can be elaborated with this method. If the
// is_force flag is true, then the set of valid l-value types
// is slightly modified to accomodate the Verilog force
// is slightly modified to accommodate the Verilog force
// statement
virtual NetAssign_* elaborate_lval(Design*des,
NetScope*scope,
@ -255,7 +255,7 @@ class PEIdent : public PExpr {
explicit PEIdent(const pform_name_t&);
~PEIdent();
// Add another name to the string of heirarchy that is the
// Add another name to the string of hierarchy that is the
// current identifier.
void append_name(perm_string);
@ -551,7 +551,7 @@ class PEBinary : public PExpr {
NetEBinary*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetEBinary*elaborate_eval_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
static void surpress_operand_sign_if_needed_(NetExpr*lp, NetExpr*rp);
static void suppress_operand_sign_if_needed_(NetExpr*lp, NetExpr*rp);
private:
NetNet* elaborate_net_add_(Design*des, NetScope*scope,
@ -597,7 +597,7 @@ class PEBinary : public PExpr {
};
/*
* Here are a few specilized classes for handling specific binary
* Here are a few specialized classes for handling specific binary
* operators.
*/
class PEBComp : public PEBinary {
@ -667,7 +667,7 @@ class PETernary : public PExpr {
class PECallFunction : public PExpr {
public:
explicit PECallFunction(const pform_name_t&n, const svector<PExpr *> &parms);
// Call of system function (name is not heirarchical)
// Call of system function (name is not hierarchical)
explicit PECallFunction(perm_string n, const svector<PExpr *> &parms);
explicit PECallFunction(perm_string n);
~PECallFunction();

4
elab_expr.cc
View File

@ -114,7 +114,7 @@ NetEBinary* PEBinary::elaborate_expr(Design*des, NetScope*scope,
return tmp;
}
void PEBinary::surpress_operand_sign_if_needed_(NetExpr*lp, NetExpr*rp)
void PEBinary::suppress_operand_sign_if_needed_(NetExpr*lp, NetExpr*rp)
{
// If either operand is unsigned, then treat the whole
// expression as unsigned. This test needs to be done here
@ -313,7 +313,7 @@ NetEBinary* PEBComp::elaborate_expr(Design*des, NetScope*scope,
return 0;
}
surpress_operand_sign_if_needed_(lp, rp);
suppress_operand_sign_if_needed_(lp, rp);
return elaborate_eval_expr_base_(des, lp, rp, use_wid);
}

2
elab_net.cc
View File

@ -1323,7 +1323,7 @@ NetNet* PECallFunction::elaborate_net(Design*des, NetScope*scope,
NetScope*dscope = def->scope();
assert(dscope);
/* This must be a ufuction that returns a signal. */
/* This must be a function that returns a signal. */
assert(def->return_sig());
/* check the validity of the parameters. */

2
elab_sig.cc
View File

@ -55,7 +55,7 @@ static bool signal_is_in_port(const svector<Module::port_t*>&ports,
// the port has 0 or more NetEIdent objects concatenated
// together that form the port.
// Note that module ports should not have any heirarchy
// Note that module ports should not have any hierarchy
// in their names: they are in the root of the module
// scope by definition.

2
elaborate.cc
View File

@ -2843,7 +2843,7 @@ NetProc* PForever::elaborate(Design*des, NetScope*scope) const
*
* The <lval> can be anything that a normal behavioral assignment can
* take, plus net signals. This is a little bit more lax then the
* other proceedural assignments.
* other procedural assignments.
*/
NetForce* PForce::elaborate(Design*des, NetScope*scope) const
{

20
ivl_target.h
View File

@ -395,7 +395,7 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
* This returns the nexus that tracks the condition for the
* delay. If the delay path is unconditional, this returns nil.
*
* ivl_path_srouce_posedge
* ivl_path_source_posedge
* ivl_path_source_negedge
* These functions return true if the source is edge sensitive.
*/
@ -469,7 +469,7 @@ extern ivl_net_const_t ivl_design_const(ivl_design_t, unsigned idx);
* The is the type of the node.
*
* ivl_const_bits
* This returns a pointer to an array of conststant characters,
* This returns a pointer to an array of constant characters,
* each byte a '0', '1', 'x' or 'z'. The array is *not* nul
* terminated.
*
@ -743,7 +743,7 @@ extern unsigned ivl_file_table_size(void);
* SEMANTIC NOTES
* The ivl_logic_width applies to all the pins of a logic device. If a
* logic device has width, that means that it is actually an array of
* logic devices tha each process a bit slice of the
* logic devices that each process a bit slice of the
* inputs/output. That implies that the widths of all the inputs and
* the output must be identical.
*
@ -925,7 +925,7 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
* The ivl_lpm_q nexus is the output from the concatenation.
*
* The ivl_lpm_data function returns the connections for the inputs to
* the concatentation. The ivl_lpm_size function returns the number of
* the concatenation. The ivl_lpm_size function returns the number of
* inputs help by the device.
*
* - Divide (IVL_LPM_DIVIDE)
@ -999,7 +999,7 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
* The ivl_lpm_data() method returns the inputs of the MUX device. The
* ivl_lpm_size() method returns the number of data inputs there
* are. All the data inputs have the same width, the width of the
* ivl_lpm_q output. The type of the device is devined from the
* ivl_lpm_q output. The type of the device is divined from the
* inputs and the Q. All the types must be exactly the same.
*
* - D-FlipFlop (IVL_LPM_FF)
@ -1052,7 +1052,7 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
* output, but the distance has its own width.
*
* The ivl_lpm_signed() flag means for IVL_LPM_SHIFTR that the right
* shift is *signed*. For SHIFTL, then signed-ness is emaningless.
* shift is *signed*. For SHIFTL, then signed-ness is meaningless.
*
* - System function call (IVL_LPM_SFUNC)
* This device represents a netlist call to a system function. The
@ -1073,8 +1073,8 @@ extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
* function are connected to the net, as is the output.
*
* The function definition is associated with a scope, and the
* ivl_lpm_define fuction returns the scope that is that definition.
* See the ivl_scope_* fuctions for how to get at the actual
* ivl_lpm_define function returns the scope that is that definition.
* See the ivl_scope_* functions for how to get at the actual
* definition.
*
* As with many LPM nodes, the ivl_lpm_q function returns the nexus
@ -1193,7 +1193,7 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
* an expression that calculates the address of the array word. If
* the referenced signal has more than one word, this expression must
* be present. If the signal has exactly one word (it is not an array)
* then the ivl_lval_idx exression must *not* be present.
* then the ivl_lval_idx expression must *not* be present.
*
* For array words, the ivl_lval_width is the width of the word.
*/
@ -1489,7 +1489,7 @@ extern int ivl_scope_time_units(ivl_scope_t net);
* ivl_signal_array_count
* The signal may be arrayed. If so, the array_count is >1. Each
* word of the array has its own nexus. The array_base is the
* address is the Verilg source for the canonical zero word. This
* address is the Verilog source for the canonical zero word. This
* may be negative, positive or zero.
*
* Note that arraying of the signal into words is distinct from the

6
netlist.h
View File

@ -740,7 +740,7 @@ class NetCompare : public NetNode {
* with pin-1 at the LSB, pin-2 next, and so on. This node is most
* like the NetLogic node, as it has one output at pin 0 and the
* remaining pins are the input that are combined to make the
* output. It is seperated out because it it generally a special case
* output. It is separated out because it it generally a special case
* for the code generators.
*
* When constructing the node, the width is the vector_width of the
@ -993,7 +993,7 @@ class NetMux : public NetNode {
* output, and the rpt is the repeat count. The wid must be an even
* multiple of the cnt, and wid/cnt is the expected input width.
*
* The device has exacly 2 pins: pin(0) is the output and pin(1) the
* The device has exactly 2 pins: pin(0) is the output and pin(1) the
* input.
*/
class NetReplicate : public NetNode {
@ -1441,7 +1441,7 @@ class NetLiteral : public NetNode {
* of that value that is important.
*
* All these devices process vectors bitwise, so each bit can be
* logically seperated. The exception is the CONCAT gate, which is
* logically separated. The exception is the CONCAT gate, which is
* really an abstract gate that takes the inputs and turns it into a
* vector of bits.
*/

42
parse.y
View File

@ -221,7 +221,7 @@ static inline void FILE_NAME(LineInfo*tmp, const struct vlltype&where)
%type <gate> gate_instance
%type <gates> gate_instance_list
%type <pform_name> heirarchy_identifier
%type <pform_name> hierarchy_identifier
%type <expr> expression expr_primary expr_mintypmax
%type <expr> lpvalue
%type <expr> delay_value delay_value_simple
@ -488,7 +488,7 @@ charge_strength_opt
;
defparam_assign
: heirarchy_identifier '=' expression
: hierarchy_identifier '=' expression
{ PExpr*tmp = $3;
if (!pform_expression_is_constant(tmp)) {
yyerror(@3, "error: parameter value "
@ -664,7 +664,7 @@ dr_strength1
;
event_control
: '@' heirarchy_identifier
: '@' hierarchy_identifier
{ PEIdent*tmpi = new PEIdent(*$2);
PEEvent*tmpe = new PEEvent(PEEvent::ANYEDGE, tmpi);
PEventStatement*tmps = new PEventStatement(tmpe);
@ -1028,10 +1028,10 @@ expr_primary
delete $1;
}
/* The heirarchy_identifier rule matches simple identifiers as well as
/* The hierarchy_identifier rule matches simple identifiers as well as
indexed arrays and part selects */
| heirarchy_identifier
| hierarchy_identifier
{ PEIdent*tmp = new PEIdent(*$1);
FILE_NAME(tmp, @1);
$$ = tmp;
@ -1042,7 +1042,7 @@ expr_primary
function call. If a system identifier, then a system function
call. */
| heirarchy_identifier '(' expression_list_proper ')'
| hierarchy_identifier '(' expression_list_proper ')'
{ PECallFunction*tmp = new PECallFunction(*$1, *$3);
FILE_NAME(tmp, @1);
delete $1;
@ -1305,19 +1305,19 @@ gatetype
hierarchical name from the left to the right, forming a list of
names. */
heirarchy_identifier
hierarchy_identifier
: IDENTIFIER
{ $$ = new pform_name_t;
$$->push_back(name_component_t(lex_strings.make($1)));
delete $1;
}
| heirarchy_identifier '.' IDENTIFIER
| hierarchy_identifier '.' IDENTIFIER
{ pform_name_t * tmp = $1;
tmp->push_back(name_component_t(lex_strings.make($3)));
delete $3;
$$ = tmp;
}
| heirarchy_identifier '[' expression ']'
| hierarchy_identifier '[' expression ']'
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
@ -1326,7 +1326,7 @@ heirarchy_identifier
tail.index.push_back(itmp);
$$ = tmp;
}
| heirarchy_identifier '[' expression ':' expression ']'
| hierarchy_identifier '[' expression ':' expression ']'
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
@ -1336,7 +1336,7 @@ heirarchy_identifier
tail.index.push_back(itmp);
$$ = tmp;
}
| heirarchy_identifier '[' expression K_PO_POS expression ']'
| hierarchy_identifier '[' expression K_PO_POS expression ']'
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
@ -1346,7 +1346,7 @@ heirarchy_identifier
tail.index.push_back(itmp);
$$ = tmp;
}
| heirarchy_identifier '[' expression K_PO_NEG expression ']'
| hierarchy_identifier '[' expression K_PO_NEG expression ']'
{ pform_name_t * tmp = $1;
name_component_t&tail = tmp->back();
index_component_t itmp;
@ -1557,7 +1557,7 @@ signed_opt : K_signed { $$ = true; } | {$$ = false; } ;
assignments. It is more limited then the general expr_primary
rule to reflect the rules for assignment l-values. */
lpvalue
: heirarchy_identifier
: hierarchy_identifier
{ PEIdent*tmp = new PEIdent(*$1);
FILE_NAME(tmp, @1);
$$ = tmp;
@ -2892,11 +2892,11 @@ spec_notifier_opt
spec_notifier
: ','
{ }
| ',' heirarchy_identifier
| ',' hierarchy_identifier
{ delete $2; }
| spec_notifier ','
{ }
| spec_notifier ',' heirarchy_identifier
| spec_notifier ',' hierarchy_identifier
{ delete $3; }
| IDENTIFIER
{ delete $1; }
@ -3003,13 +3003,13 @@ statement
$$ = tmp;
}
| K_disable heirarchy_identifier ';'
| K_disable hierarchy_identifier ';'
{ PDisable*tmp = new PDisable(*$2);
FILE_NAME(tmp, @1);
delete $2;
$$ = tmp;
}
| K_TRIGGER heirarchy_identifier ';'
| K_TRIGGER hierarchy_identifier ';'
{ PTrigger*tmp = new PTrigger(*$2);
FILE_NAME(tmp, @1);
delete $2;
@ -3210,7 +3210,7 @@ statement
delete $1;
$$ = tmp;
}
| heirarchy_identifier '(' expression_list_proper ')' ';'
| hierarchy_identifier '(' expression_list_proper ')' ';'
{ PCallTask*tmp = new PCallTask(*$1, *$3);
FILE_NAME(tmp, @1);
delete $1;
@ -3222,14 +3222,14 @@ statement
between parentheses, but it seems natural, and people commonly
want it. So accept it explicitly. */
| heirarchy_identifier '(' ')' ';'
| hierarchy_identifier '(' ')' ';'
{ svector<PExpr*>pt (0);
PCallTask*tmp = new PCallTask(*$1, pt);
FILE_NAME(tmp, @1);
delete $1;
$$ = tmp;
}
| heirarchy_identifier ';'
| hierarchy_identifier ';'
{ svector<PExpr*>pt (0);
PCallTask*tmp = new PCallTask(*$1, pt);
FILE_NAME(tmp, @1);
@ -3649,7 +3649,7 @@ udp_output_sym
/* Port declarations create wires for the inputs and the output. The
makes for these ports are scoped within the UDP, so there is no
heirarchy involved. */
hierarchy involved. */
udp_port_decl
: K_input list_of_identifiers ';'
{ $$ = pform_make_udp_input_ports($2); }

2
pform.cc
View File

@ -507,7 +507,7 @@ static void process_udp_table(PUdp*udp, list<string>*table,
placed in the PUdp object.
The table strings are made up by the parser to be two or
three substrings seperated by ';', i.e.:
three substrings separated by ';', i.e.:
0101:1:1 (synchronous device entry)
0101:0 (combinational device entry)

2
pform_types.h
View File

@ -53,7 +53,7 @@ struct name_component_t {
extern bool operator < (const name_component_t&lef, const name_component_t&rig);
/*
* The pform_name_t is the general form for a heirarchical identifier.
* The pform_name_t is the general form for a hierarchical identifier.
*/
typedef std::list<name_component_t> pform_name_t;

2
synth2.cc
View File

@ -548,7 +548,7 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, NetFF*ff,
/* XXXX I really should find a way to check that the
edge used on the reset input is correct. This would
involve interpreting the exression that is fed by the
involve interpreting the expression that is fed by the
reset expression. */
//assert(ev->edge() == NetEvProbe::POSEDGE);

4
t-dll.h
View File

@ -446,7 +446,7 @@ struct ivl_net_logic_s {
struct ivl_udp_s {
perm_string name;
unsigned nin;
int sequ; /* boolen */
int sequ; /* boolean */
char init;
unsigned nrows;
typedef const char*ccharp_t;
@ -483,7 +483,7 @@ struct ivl_nexus_ptr_s {
# define __NEXUS_PTR_LPM 3
/*
* NOTE: ONLY allocat ivl_nexus_s objects with the included "new" operator.
* NOTE: ONLY allocate ivl_nexus_s objects with the included "new" operator.
*/
struct ivl_nexus_s {
unsigned nptr_;

10
tgt-stub/stub.c
View File

@ -504,7 +504,7 @@ static void show_lpm_part(ivl_lpm_t net)
}
if (width_of_nexus(ivl_lpm_q(net,0)) != width) {
fprintf(out, " ERROR: Part select input mistatch."
fprintf(out, " ERROR: Part select input mismatch."
" Nexus width=%u, expect width=%u\n",
width_of_nexus(ivl_lpm_q(net,0)), width);
stub_errors += 1;
@ -520,7 +520,7 @@ static void show_lpm_part(ivl_lpm_t net)
}
if (width_of_nexus(ivl_lpm_data(net,0)) != width) {
fprintf(out, " ERROR: Part select input mistatch."
fprintf(out, " ERROR: Part select input mismatch."
" Nexus width=%u, expect width=%u\n",
width_of_nexus(ivl_lpm_data(net,0)), width);
stub_errors += 1;
@ -556,7 +556,7 @@ static void show_lpm_part_bi(ivl_lpm_t net)
/* The Q vector must be exactly the width of the part select. */
if (width_of_nexus(ivl_lpm_q(net,0)) != width) {
fprintf(out, " ERROR: Part select input mistatch."
fprintf(out, " ERROR: Part select input mismatch."
" Nexus width=%u, expect width=%u\n",
width_of_nexus(ivl_lpm_q(net,0)), width);
stub_errors += 1;
@ -644,7 +644,7 @@ static void show_lpm_repeat(ivl_lpm_t net)
stub_errors += 1;
} else if (width/count != width_of_nexus(nex_a)) {
fprintf(out, " ERROR: Windth of D is %u, expecting %u\n",
fprintf(out, " ERROR: Width of D is %u, expecting %u\n",
width_of_nexus(nex_a), width/count);
stub_errors += 1;
}
@ -1447,7 +1447,7 @@ static void show_primitive(ivl_udp_t net, unsigned ref_count)
{
unsigned rdx;
fprintf(out, "primtive %s (referenced %u times)\n",
fprintf(out, "primitive %s (referenced %u times)\n",
ivl_udp_name(net), ref_count);
if (ivl_udp_sequ(net))