Clean up warnings that add_sub got from Alliance
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steve
parent
16f7268729
commit
477495c648
255
t-xnf.cc
255
t-xnf.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: t-xnf.cc,v 1.15 1999/11/06 04:51:42 steve Exp $"
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#ident "$Id: t-xnf.cc,v 1.16 1999/11/17 01:31:28 steve Exp $"
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#endif
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/* XNF BACKEND
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@ -93,6 +93,10 @@ class target_xnf : public target_t {
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const NetObj::Link&lnk);
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static void draw_sym_with_lcaname(ostream&os, string lca,
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const NetNode*net);
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static void draw_xor(ostream&os, const NetAddSub*, unsigned idx);
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enum adder_type {FORCE0, LOWER, UPPER, DOUBLE };
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static void draw_carry(ostream&os, const NetAddSub*, unsigned idx,
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enum adder_type);
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ofstream ncf_;
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};
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@ -285,6 +289,112 @@ void target_xnf::signal(ostream&os, const NetNet*net)
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<< endl;
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}
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void target_xnf::draw_xor(ostream &os, const NetAddSub*gate, unsigned idx)
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{
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string name = mangle(gate->name());
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string name_add = name;
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string name_cout = name + "/COUT";
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// We only need to pick up the
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// carry if we are not the 0 bit. (We know it is 0).
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os << "SYM, " << name_add << "<" << (idx+0) << ">, XOR, "
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"LIBVER=2.0.0" << endl;
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draw_pin(os, "O", gate->pin_Result(idx));
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draw_pin(os, "I0", gate->pin_DataA(idx));
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draw_pin(os, "I1", gate->pin_DataB(idx));
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if (idx > 0) {
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os << " PIN, I2, I, " << name_cout << "<" <<
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idx << ">" << endl;
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}
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os << "END" << endl;
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}
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void target_xnf::draw_carry(ostream &os, const NetAddSub*gate, unsigned idx,
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enum adder_type type)
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{
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string name = mangle(gate->name());
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string name_cy4 = name + "/CY";
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string name_cym = name + "/CM";
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string name_cout = name + "/COUT";
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os << "SYM, " << name_cy4 << "<" << idx << ">, CY4, "
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"LIBVER=2.0.0" << endl;
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// Less significant bit addends, if any
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if ( type == LOWER || type == DOUBLE ) {
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draw_pin(os, "A0", gate->pin_DataA(idx));
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draw_pin(os, "B0", gate->pin_DataB(idx));
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}
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// More significant bit addends, if any
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if ( type == UPPER || type == DOUBLE ) {
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unsigned int i = (type==UPPER)?idx:(idx+1);
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draw_pin(os, "A1", gate->pin_DataA(i));
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draw_pin(os, "B1", gate->pin_DataB(i));
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}
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// Carry input
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if ( type != FORCE0 && type != UPPER ) {
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os << " PIN, CIN, I, " << name_cout << "<" <<
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idx << ">" << endl;
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}
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// Connect the Cout0 to a signal so that I can connect
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// it to the adder.
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if ( type == LOWER || type == DOUBLE ) {
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os << " PIN, COUT0, O, " << name_cout << "<" << (idx+1) <<
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">" << endl;
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}
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// Connect the Cout, this will connect to the next Cin
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if ( type == FORCE0 || type == UPPER || type == DOUBLE ) {
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unsigned int to = (type==FORCE0)?(0):(idx+2);
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if (type==UPPER) to=idx+1;
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os << " PIN, COUT, O, " << name_cout << "<" << to <<
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">" << endl;
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}
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// Carry In for mode UPPER comes from a strange place
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if ( type == UPPER ) {
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os << " PIN, A0, I, " << name_cout << "<dummy>" << endl;
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}
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// These are the mode inputs from the CY_xx pseudo-device
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", I, " << name << "/C"
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<< cn << "<" << (idx) << ">" << endl;
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}
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os << "END" << endl;
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// Complete the dummy force used above
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if ( type == UPPER ) {
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os << "PWR, 0, " << name_cout << "<dummy>" << endl;
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}
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// On to the CY_xx pseudo-device itself
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os << "SYM, " << name_cym << "<" << (idx) << ">, ";
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switch (type) {
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case FORCE0:
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os << "CY4_37, CYMODE=FORCE-0" << endl;
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break;
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case LOWER:
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os << "CY4_01, CYMODE=ADD-F-CI" << endl;
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break;
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case UPPER:
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os << "CY4_03, CYMODE=ADD-G-F1" << endl;
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break;
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case DOUBLE:
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os << "CY4_02, CYMODE=ADD-FG-CI" << endl;
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break;
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}
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", O, " << name << "/C"
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<< cn << "<" << (idx) << ">" << endl;
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}
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os << "END" << endl;
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}
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/*
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* This function makes an adder out of carry logic symbols. It makes
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* as many 2 bit adders as are possible, then the top bit is made into
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@ -296,147 +406,37 @@ void target_xnf::signal(ostream&os, const NetNet*net)
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* References:
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* XNF 6.1 Specification
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* Application note XAPP013
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* Xilinx Libraries Guide, Chapter 12
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*/
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void target_xnf::lpm_add_sub(ostream&os, const NetAddSub*gate)
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{
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// Keep people from thinking this really works.
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//assert(0);
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unsigned width = gate->width();
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string name = mangle(gate->name());
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string name_add = name;
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string name_cy4 = name + "/CY";
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string name_cym = name + "/CM";
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string name_cout = name + "/COUT";
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// Don't handle carry output yet
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// assert (count_outputs(gate->pin_Cout())==0);
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unsigned carry_width = width-1;
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/* Make the force-0 cary mode object to initialize the bottom
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bits of the carry chain. Label this with the width instead
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of the bit position so that symbols dont clash. */
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os << "SYM, " << name_cy4 << "<" << width << ">, CY4, "
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"LIBVER=2.0.0" << endl;
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os << " PIN, COUT, O, " << name_cout << "<" << width << ">" << endl;
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", I, " << name << "/C"
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<< cn << "<" << width << ">" << endl;
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of the bit position so that symbols don't clash. */
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if (carry_width%2) {
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draw_carry(os, gate, width, FORCE0);
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} else {
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draw_carry(os, gate, 0, UPPER);
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}
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os << "END" << endl;
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os << "SYM, " << name_cym << "<" << width << ">, CY4_37, "
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"CYMODE=FORCE-0" << endl;
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", O, " << name << "/C"
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<< cn << "<" << width << ">" << endl;
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}
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os << "END" << endl;
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/* Now make the 2 bit adders that chain from the cin
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initializer and up. Save the tail bit (if there is one) for
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later. */
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for (unsigned idx = 0 ; idx < (width&~1) ; idx += 2) {
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os << "SYM, " << name_cy4 << "<" << idx << ">, CY4, "
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"LIBVER=2.0.0" << endl;
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draw_pin(os, "A0", gate->pin_DataA(idx+0));
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draw_pin(os, "B0", gate->pin_DataB(idx+0));
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draw_pin(os, "A1", gate->pin_DataA(idx+1));
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draw_pin(os, "B1", gate->pin_DataB(idx+1));
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// Connect the Cout0 to a signal so that I can connect
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// it to the adder.
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os << " PIN, COUT0, O, " << name_cout << "<" << idx <<
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">" << endl;
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// Connect the Cout to the next Cin
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if ((idx+2) < width)
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os << " PIN, COUT, O, " << name_cout << "<" <<
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(idx+1) << ">" << endl;
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// Connect the Cin to the previous Cout
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if (idx > 0)
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os << " PIN, CIN, I, " << name_cout << "<" <<
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(idx-1) << ">" << endl;
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else
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os << " PIN, CIN, I, " << name_cout << "<" <<
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(width) << ">" << endl;
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", I, " << name << "/C"
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<< cn << "<" << idx << ">" << endl;
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}
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os << "END" << endl;
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os << "SYM, " << name_cym << "<" << idx << ">, ";
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os << "CY4_02, CYMODE=ADD-FG-CI" << endl;
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", O, " << name << "/C"
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<< cn << "<" << idx << ">" << endl;
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}
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os << "END" << endl;
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// Draw the first bit adder. We only need to pick up the
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// carry if we are not the 0 bit. (We know it is 0).
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os << "SYM, " << name_add << "<" << (idx+0) << ">, XOR, "
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"LIBVER=2.0.0" << endl;
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draw_pin(os, "O", gate->pin_Result(idx));
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draw_pin(os, "I0", gate->pin_DataA(idx));
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draw_pin(os, "I1", gate->pin_DataB(idx));
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if (idx > 0) {
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os << " PIN, I2, I, " << name_cout << "<" <<
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(idx-1) << ">" << endl;
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}
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os << "END" << endl;
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// Draw the second bit adder. This gets the carry from
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// the first bit CY4.
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os << "SYM, " << name_add << "<" << (idx+1) << ">, XOR, "
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"LIBVER=2.0.0" << endl;
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draw_pin(os, "O", gate->pin_Result(idx+1));
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draw_pin(os, "I0", gate->pin_DataA(idx+1));
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draw_pin(os, "I1", gate->pin_DataB(idx+1));
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os << " PIN, I2, I, " << name_cout << "<" << idx << ">"
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<< endl;
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os << "END" << endl;
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for (unsigned idx = 1-(carry_width%2) ; idx < carry_width-1 ; idx += 2) {
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draw_carry(os, gate, idx, DOUBLE);
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}
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/* If there is a tail bit, draw it as a single bit adder that
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takes its carry in from the previously drawn adder. */
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if (width%2) {
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os << "SYM, " << name_cy4 << "<" << (width-1) << ">, CY4, "
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"LIBVER=2.0.0" << endl;
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/* Always have a tail bit */
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draw_carry(os, gate, carry_width-1, LOWER);
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draw_pin(os, "A0", gate->pin_DataA(width-1));
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draw_pin(os, "B0", gate->pin_DataB(width-1));
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if (width > 2)
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os << " PIN, CIN, I, " << name_cout << "<" <<
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(width-2) << ">" << endl;
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", I, " << name << "/C"
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<< cn << "<" << (width-1) << ">" << endl;
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}
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os << "END" << endl;
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os << "SYM, " << name_cym << "<" << (width-1) << ">, ";
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os << "CY4_01, CYMODE=ADD-F-CI" << endl;
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for (unsigned cn = 0 ; cn < 8 ; cn += 1) {
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os << " PIN, C" << cn << ", O, " << name << "/C"
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<< cn << "<" << (width-1) << ">" << endl;
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}
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os << "END" << endl;
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os << "SYM, " << name_add << "<" << (width-1) << ">, XOR, "
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"LIBVER=2.0.0" << endl;
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draw_pin(os, "O", gate->pin_Result(width-1));
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draw_pin(os, "I0", gate->pin_DataA(width-1));
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draw_pin(os, "I1", gate->pin_DataB(width-1));
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os << " PIN, I2, I, " << name_cout << "<" << (width-2) << ">"
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<< endl;
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os << "END" << endl;
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for (unsigned idx = 0 ; idx < width ; ++idx) {
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draw_xor(os, gate, idx);
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}
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}
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@ -615,6 +615,9 @@ extern const struct target tgt_xnf = { "xnf", &target_xnf_obj };
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/*
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* $Log: t-xnf.cc,v $
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* Revision 1.16 1999/11/17 01:31:28 steve
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* Clean up warnings that add_sub got from Alliance
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*
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* Revision 1.15 1999/11/06 04:51:42 steve
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* Support writing some XNF things into an NCF file.
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*
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