Handle statements in blocks overriding previous statement outputs.
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c30cd9afea
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4644c220e8
39
synth2.cc
39
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.39 2004/10/04 01:10:55 steve Exp $"
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#ident "$Id: synth2.cc,v 1.39.2.1 2005/08/21 22:49:54 steve Exp $"
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#endif
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# include "config.h"
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@ -143,6 +143,11 @@ bool NetBlock::synth_async(Design*des, NetScope*scope,
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const perm_string tmp1 = perm_string::literal("tmp1");
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const perm_string tmp2 = perm_string::literal("tmp2");
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const perm_string tmp3 = perm_string::literal("tmp3");
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NetNet*accum_out = new NetNet(scope, tmp3, NetNet::WIRE,
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nex_out->pin_count());
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accum_out->local_flag(true);
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bool flag = true;
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NetProc*cur = last_;
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@ -168,18 +173,42 @@ bool NetBlock::synth_async(Design*des, NetScope*scope,
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if (ok_flag == false)
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continue;
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NetNet*new_accum = new NetNet(scope, tmp3, NetNet::WIRE,
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nex_out->pin_count());
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/* Use the nex_map to link up the output from the
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substatement to the output of the block as a whole. */
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for (unsigned idx = 0 ; idx < tmp_out->pin_count() ; idx += 1) {
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unsigned ptr = find_nexus_in_set(nex_map, tmp_set[idx]);
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connect(nex_out->pin(ptr), tmp_out->pin(idx));
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connect(new_accum->pin(ptr), tmp_out->pin(idx));
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}
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delete tmp_map;
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delete tmp_out;
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/* Anything that is not redriven by the current
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statement inherits the value that was driven from any
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previous statements. */
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for (unsigned idx = 0; idx < new_accum->pin_count(); idx += 1) {
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if (new_accum->pin(idx).is_linked())
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continue;
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connect(new_accum->pin(idx), accum_out->pin(idx));
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}
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delete accum_out;
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accum_out = new_accum;
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} while (cur != last_);
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/* Now bind the accumulated output valies to the nex_out
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passed in. Note that each previous step has already did the
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pin mapping, so just connect. */
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for (unsigned idx = 0 ; idx < accum_out->pin_count() ; idx += 1) {
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connect(nex_out->pin(idx), accum_out->pin(idx));
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}
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delete accum_out;
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DEBUG_SYNTH2_EXIT("NetBlock",flag)
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return flag;
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}
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@ -299,6 +328,9 @@ bool NetCase::synth_async(Design*des, NetScope*scope,
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/* Missing case and no default; this could still be
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* synthesizable with synchronous logic, but not here. */
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DEBUG_SYNTH2_EXIT("NetCase", false)
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cerr << get_line()
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<< ": error: Incomplete case statement"
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<< " is missing a default case." << endl;
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return false;
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}
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statement_map[item]->synth_async(des, scope, nex_map, sig);
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@ -985,6 +1017,9 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.39.2.1 2005/08/21 22:49:54 steve
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* Handle statements in blocks overriding previous statement outputs.
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*
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* Revision 1.39 2004/10/04 01:10:55 steve
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* Clean up spurious trailing white space.
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*
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